riscv: dts: jh7110: Add ethernet device tree nodes

Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa..3c1148a 100644 (file)
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
                i2c2 = &i2c2;
                i2c5 = &i2c5;
                i2c6 = &i2c6;
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
        };
 
        chosen {
@@ -317,3 +319,35 @@
        assigned-clock-parents = <&osc>;
        assigned-clock-rates = <0>;
 };
+
+&gmac0 {
+       phy-handle = <&phy0>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "snps,dwmac-mdio";
+
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+               };
+       };
+};
+
+&gmac1 {
+       phy-handle = <&phy1>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "snps,dwmac-mdio";
+
+               phy1: ethernet-phy@1 {
+                       reg = <0>;
+               };
+       };
+};

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879..58e332e 100644 (file)
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -235,6 +235,13 @@
                #clock-cells = <0>;
        };
 
+       stmmac_axi_setup: stmmac-axi-config {
+               snps,lpi_en;
+               snps,wr_osr_lmt = <4>;
+               snps,rd_osr_lmt = <4>;
+               snps,blen = <256 128 64 32 0 0 0>;
+       };
+
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&plic>;
@@ -539,6 +546,68 @@
                        status = "disabled";
                };
 
+               gmac0: ethernet@16030000 {
+                       compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+                       reg = <0x0 0x16030000 0x0 0x10000>;
+                       clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
+                                <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
+                                <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
+                                <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
+                                <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
+                       clock-names = "stmmaceth", "pclk", "ptp_ref",
+                                     "tx", "gtx";
+                       resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
+                                <&aoncrg JH7110_AONRST_GMAC0_AHB>;
+                       reset-names = "stmmaceth", "ahb";
+                       interrupts = <7>, <6>, <5>;
+                       interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+                       snps,multicast-filter-bins = <64>;
+                       snps,perfect-filter-entries = <8>;
+                       rx-fifo-depth = <2048>;
+                       tx-fifo-depth = <2048>;
+                       snps,fixed-burst;
+                       snps,no-pbl-x8;
+                       snps,force_thresh_dma_mode;
+                       snps,axi-config = <&stmmac_axi_setup>;
+                       snps,tso;
+                       snps,en-tx-lpi-clockgating;
+                       snps,txpbl = <16>;
+                       snps,rxpbl = <16>;
+                       starfive,syscon = <&aon_syscon 0xc 0x12>;
+                       status = "disabled";
+               };
+
+               gmac1: ethernet@16040000 {
+                       compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+                       reg = <0x0 0x16040000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
+                                <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
+                                <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
+                                <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
+                                <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
+                       clock-names = "stmmaceth", "pclk", "ptp_ref",
+                                     "tx", "gtx";
+                       resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
+                                <&syscrg JH7110_SYSRST_GMAC1_AHB>;
+                       reset-names = "stmmaceth", "ahb";
+                       interrupts = <78>, <77>, <76>;
+                       interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+                       snps,multicast-filter-bins = <64>;
+                       snps,perfect-filter-entries = <8>;
+                       rx-fifo-depth = <2048>;
+                       tx-fifo-depth = <2048>;
+                       snps,fixed-burst;
+                       snps,no-pbl-x8;
+                       snps,force_thresh_dma_mode;
+                       snps,axi-config = <&stmmac_axi_setup>;
+                       snps,tso;
+                       snps,en-tx-lpi-clockgating;
+                       snps,txpbl = <16>;
+                       snps,rxpbl = <16>;
+                       starfive,syscon = <&sys_syscon 0x90 0x2>;
+                       status = "disabled";
+               };
+
                aoncrg: clock-controller@17000000 {
                        compatible = "starfive,jh7110-aoncrg";
                        reg = <0x0 0x17000000 0x0 0x10000>;