i965: Use align1 mode for barrier messages.

In commit 7428e6f86ab5 we switched the barrier SEND message's
destination type to UW to avoid problems in SIMD16 compute shaders.

Tessellation control shaders also use barriers, and in vec4 mode, we
were emitting them in align16 mode.  The simulator warns that only UD,
D, F, and DF are valid destination types - UW is technically illegal.

So, switch to align1 mode.  Either mode should work fine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 8536a13..05c097f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -3587,6 +3587,8 @@ brw_barrier(struct brw_codegen *p, struct brw_reg src)
 
    assert(devinfo->gen >= 7);
 
+   brw_push_insn_state(p);
+   brw_set_default_access_mode(p, BRW_ALIGN_1);
    inst = next_insn(p, BRW_OPCODE_SEND);
    brw_set_dest(p, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
    brw_set_src0(p, inst, src);
@@ -3603,6 +3605,7 @@ brw_barrier(struct brw_codegen *p, struct brw_reg src)
                                   BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG);
 
    brw_inst_set_mask_control(devinfo, inst, BRW_MASK_DISABLE);
+   brw_pop_insn_state(p);
 }