};
const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
- .cfg = exynos7_ufs_phy_cfgs,
+ .cfgs = exynos7_ufs_phy_cfgs,
.isol = {
.offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
.mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
};
const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
- .cfg = exynosautov9_ufs_phy_cfgs,
+ .cfgs = exynosautov9_ufs_phy_cfgs,
.isol = {
.offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL,
.mask = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK,
static int samsung_ufs_phy_calibrate(struct phy *phy)
{
struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
- struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
+ struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfgs;
const struct samsung_ufs_phy_cfg *cfg;
int err = 0;
int i;
drvdata = match->data;
phy->dev = dev;
phy->drvdata = drvdata;
- phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg;
+ phy->cfgs = (struct samsung_ufs_phy_cfg **)drvdata->cfgs;
phy->isol = &drvdata->isol;
phy->lane_cnt = PHY_DEF_LANE_CNT;
};
struct samsung_ufs_phy_drvdata {
- const struct samsung_ufs_phy_cfg **cfg;
+ const struct samsung_ufs_phy_cfg **cfgs;
struct pmu_isol {
u32 offset;
u32 mask;
struct clk *rx0_symbol_clk;
struct clk *rx1_symbol_clk;
const struct samsung_ufs_phy_drvdata *drvdata;
- struct samsung_ufs_phy_cfg **cfg;
+ struct samsung_ufs_phy_cfg **cfgs;
const struct pmu_isol *isol;
u8 lane_cnt;
int ufs_phy_state;