#define ARITH_XOR 6
#define ARITH_CMP 7
+#define SHIFT_ROL 0
+#define SHIFT_ROR 1
#define SHIFT_SHL 4
#define SHIFT_SHR 5
#define SHIFT_SAR 7
case INDEX_op_sar_i32:
c = SHIFT_SAR;
goto gen_shift32;
-
+ case INDEX_op_rotl_i32:
+ c = SHIFT_ROL;
+ goto gen_shift32;
+ case INDEX_op_rotr_i32:
+ c = SHIFT_ROR;
+ goto gen_shift32;
+
case INDEX_op_add2_i32:
if (const_args[4])
tgen_arithi(s, ARITH_ADD, args[0], args[4]);
tcg_out_brcond2(s, args, const_args);
break;
+ case INDEX_op_bswap_i32:
+ tcg_out_opc(s, (0xc8 + args[0]) | P_EXT);
+ break;
+
+ case INDEX_op_neg_i32:
+ tcg_out_modrm(s, 0xf7, 3, args[0]);
+ break;
+
+ case INDEX_op_not_i32:
+ tcg_out_modrm(s, 0xf7, 2, args[0]);
+ break;
+
+ case INDEX_op_ext8s_i32:
+ tcg_out_modrm(s, 0xbe | P_EXT, args[0], args[1]);
+ break;
+ case INDEX_op_ext16s_i32:
+ tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
+ break;
+
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
{ INDEX_op_shl_i32, { "r", "0", "ci" } },
{ INDEX_op_shr_i32, { "r", "0", "ci" } },
{ INDEX_op_sar_i32, { "r", "0", "ci" } },
+ { INDEX_op_sar_i32, { "r", "0", "ci" } },
+ { INDEX_op_rotl_i32, { "r", "0", "ci" } },
+ { INDEX_op_rotr_i32, { "r", "0", "ci" } },
{ INDEX_op_brcond_i32, { "r", "ri" } },
{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
+ { INDEX_op_bswap_i32, { "r", "0" } },
+
+ { INDEX_op_neg_i32, { "r", "0" } },
+
+ { INDEX_op_not_i32, { "r", "0" } },
+
+ { INDEX_op_ext8s_i32, { "r", "q" } },
+ { INDEX_op_ext16s_i32, { "r", "r" } },
+
#if TARGET_LONG_BITS == 32
{ INDEX_op_qemu_ld8u, { "r", "L" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },