drm/amd/display: Program DWB watermarks from correct state

[ Upstream commit edb922b022c0c94805c4ffad202b3edff83d76f0 ]

[Why]
When diags adds a DWB via a stream update, we calculate MMHUBBUB
paramaters, but dc->current_state has not yet been updated
when the DWB programming happens. This leads to overflow on
high bandwidth tests since the incorrect MMHUBBUB arbitration
parameters are programmed.

[How]
Pass the updated context down to the (enable|update)_writeback functions
so that they can use the correct watermarks when programming MMHUBBUB.

Signed-off-by: Julian Parkin <julian.parkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index bf1d7bb..bb09243 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -423,10 +423,10 @@ bool dc_stream_add_writeback(struct dc *dc,
 
                if (dwb->funcs->is_enabled(dwb)) {
                        /* writeback pipe already enabled, only need to update */
-                       dc->hwss.update_writeback(dc, stream_status, wb_info);
+                       dc->hwss.update_writeback(dc, stream_status, wb_info, dc->current_state);
                } else {
                        /* Enable writeback pipe from scratch*/
-                       dc->hwss.enable_writeback(dc, stream_status, wb_info);
+                       dc->hwss.enable_writeback(dc, stream_status, wb_info, dc->current_state);
                }
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index b3ae1c4..937a8ba 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1356,7 +1356,8 @@ bool dcn20_update_bandwidth(
 static void dcn20_enable_writeback(
                struct dc *dc,
                const struct dc_stream_status *stream_status,
-               struct dc_writeback_info *wb_info)
+               struct dc_writeback_info *wb_info,
+               struct dc_state *context)
 {
        struct dwbc *dwb;
        struct mcif_wb *mcif_wb;
@@ -1373,7 +1374,7 @@ static void dcn20_enable_writeback(
        optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
        /* set MCIF_WB buffer and arbitration configuration */
        mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
-       mcif_wb->funcs->config_mcif_arb(mcif_wb, &dc->current_state->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
+       mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
        /* Enable MCIF_WB */
        mcif_wb->funcs->enable_mcif(mcif_wb);
        /* Enable DWB */

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 3a938cd..f6cc2d6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -321,10 +321,12 @@ struct hw_sequencer_funcs {
                        struct dc_state *context);
        void (*update_writeback)(struct dc *dc,
                        const struct dc_stream_status *stream_status,
-                       struct dc_writeback_info *wb_info);
+                       struct dc_writeback_info *wb_info,
+                       struct dc_state *context);
        void (*enable_writeback)(struct dc *dc,
                        const struct dc_stream_status *stream_status,
-                       struct dc_writeback_info *wb_info);
+                       struct dc_writeback_info *wb_info,
+                       struct dc_state *context);
        void (*disable_writeback)(struct dc *dc,
                        unsigned int dwb_pipe_inst);
 #endif