ARM: dts: armada-380.dtsi: Add definitions for PCIe legacy INTx interrupts

Add definitions for PCIe legacy INTx interrupts.

This is required for example in a scenario where a driver requests only
one of the legacy interrupts (INTA). Without this, the driver would be
notified on events on all 4 (INTA, INTB, INTC, INTD), even if it
requested only one of them.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
index cff1269..ce1dddb 100644 (file)
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -64,16 +64,26 @@
                                reg = <0x0800 0 0 0 0>;
                                #address-cells = <3>;
                                #size-cells = <2>;
+                               interrupt-names = "intx";
+                               interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
                                bus-range = <0x00 0xff>;
-                               interrupt-map-mask = <0 0 0 0>;
-                               interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-map-mask = <0 0 0 7>;
+                               interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+                                               <0 0 0 2 &pcie1_intc 1>,
+                                               <0 0 0 3 &pcie1_intc 2>,
+                                               <0 0 0 4 &pcie1_intc 3>;
                                marvell,pcie-port = <0>;
                                marvell,pcie-lane = <0>;
                                clocks = <&gateclk 8>;
                                status = "disabled";
+
+                               pcie1_intc: interrupt-controller {
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                               };
                        };
 
                        /* x1 port */
@@ -83,16 +93,26 @@
                                reg = <0x1000 0 0 0 0>;
                                #address-cells = <3>;
                                #size-cells = <2>;
+                               interrupt-names = "intx";
+                               interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
                                bus-range = <0x00 0xff>;
-                               interrupt-map-mask = <0 0 0 0>;
-                               interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-map-mask = <0 0 0 7>;
+                               interrupt-map = <0 0 0 1 &pcie2_intc 0>,
+                                               <0 0 0 2 &pcie2_intc 1>,
+                                               <0 0 0 3 &pcie2_intc 2>,
+                                               <0 0 0 4 &pcie2_intc 3>;
                                marvell,pcie-port = <1>;
                                marvell,pcie-lane = <0>;
                                clocks = <&gateclk 5>;
                                status = "disabled";
+
+                               pcie2_intc: interrupt-controller {
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                               };
                        };
 
                        /* x1 port */
@@ -102,16 +122,26 @@
                                reg = <0x1800 0 0 0 0>;
                                #address-cells = <3>;
                                #size-cells = <2>;
+                               interrupt-names = "intx";
+                               interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
                                bus-range = <0x00 0xff>;
-                               interrupt-map-mask = <0 0 0 0>;
-                               interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-map-mask = <0 0 0 7>;
+                               interrupt-map = <0 0 0 1 &pcie3_intc 0>,
+                                               <0 0 0 2 &pcie3_intc 1>,
+                                               <0 0 0 3 &pcie3_intc 2>,
+                                               <0 0 0 4 &pcie3_intc 3>;
                                marvell,pcie-port = <2>;
                                marvell,pcie-lane = <0>;
                                clocks = <&gateclk 6>;
                                status = "disabled";
+
+                               pcie3_intc: interrupt-controller {
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                               };
                        };
                };
        };