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rs6000-c: Add support for built-in functions vector signed char vec_neg (vector...
authorCarl Love <cel@us.ibm.com>
Wed, 10 May 2017 15:54:41 +0000 (15:54 +0000)
committerCarl Love <carll@gcc.gnu.org>
Wed, 10 May 2017 15:54:41 +0000 (15:54 +0000)
gcc/ChangeLog:

2017-05-10  Carl Love  <cel@us.ibm.com>

   * config/rs6000/rs6000-c: Add support for built-in functions
   vector signed char        vec_neg (vector signed char)
   vector signed short int   vec_neg (vector short int)
   vector signed int         vec_neg (vector signed int)
   vector signed long long   vec_neg (vector signed long long)
   vector float              vec_neg (vector float)
   vector double             vec_neg (vector double)
   * config/rs6000/rs6000-builtin.def: Add definitions for NEG function
   overload.
   * config/rs6000/altivec.h: Add define for vec_neg
   * doc/extend.texi: Update the built-in documentation for the
   new built-in functions.

gcc/testsuite/ChangeLog:

2017-05-10  Carl Love  <cel@us.ibm.com>
   * gcc.target/powerpc/builtins-3.c: Add tests for the new built-ins to
   to the test suite file.
   * gcc.target/powerpc/builtins-3-p8.c: Add tests for the new built-ins to
   to the test suite file.

From-SVN: r247841

gcc/ChangeLog patch | blob | history
gcc/config/rs6000/altivec.h patch | blob | history
gcc/config/rs6000/rs6000-builtin.def patch | blob | history
gcc/config/rs6000/rs6000-c.c patch | blob | history
gcc/doc/extend.texi patch | blob | history
gcc/testsuite/ChangeLog patch | blob | history
gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c patch | blob | history
gcc/testsuite/gcc.target/powerpc/builtins-3.c patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 428efba..788b333 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2017-05-10  Carl Love  <cel@us.ibm.com>
+
+       * config/rs6000/rs6000-c: Add support for built-in functions
+       vector signed char        vec_neg (vector signed char)
+       vector signed short int   vec_neg (vector short int)
+       vector signed int         vec_neg (vector signed int)
+       vector signed long long   vec_neg (vector signed long long)
+       vector float              vec_neg (vector float)
+       vector double             vec_neg (vector double)
+       * config/rs6000/rs6000-builtin.def: Add definitions for NEG function
+       overload.
+       * config/rs6000/altivec.h: Add define for vec_neg
+       * doc/extend.texi: Update the built-in documentation for the
+       new built-in functions.
+
 2017-05-10  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
 
        PR tree-optimization/77644
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index b9de05a..49b2a34 100644 (file)
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -213,6 +213,7 @@
 #define vec_lvebx __builtin_vec_lvebx
 #define vec_lvehx __builtin_vec_lvehx
 #define vec_lvewx __builtin_vec_lvewx
+#define vec_neg __builtin_vec_neg
 #define vec_pmsum_be __builtin_vec_vpmsum
 #define vec_shasigma_be __builtin_crypto_vshasigma
 /* Cell only intrinsics.  */
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index a39f936..50b1588 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1133,6 +1133,14 @@ BU_ALTIVEC_A (NABS_V16QI,     "nabs_v16qi",      CONST,  nabsv16qi2)
 BU_ALTIVEC_A (NABS_V4SF,      "nabs_v4sf",     CONST,  vsx_nabsv4sf2)
 BU_ALTIVEC_A (NABS_V2DF,      "nabs_v2df",     CONST,  vsx_nabsv2df2)
 
+/* Altivec NEG functions.  */
+BU_ALTIVEC_A (NEG_V2DI,      "neg_v2di",       CONST,  negv2di2)
+BU_ALTIVEC_A (NEG_V4SI,      "neg_v4si",       CONST,  negv4si2)
+BU_ALTIVEC_A (NEG_V8HI,      "neg_v8hi",       CONST,  negv8hi2)
+BU_ALTIVEC_A (NEG_V16QI,     "neg_v16qi",      CONST,  negv16qi2)
+BU_ALTIVEC_A (NEG_V4SF,      "neg_v4sf",       CONST,  negv4sf2)
+BU_ALTIVEC_A (NEG_V2DF,      "neg_v2df",       CONST,  negv2df2)
+
 /* 1 argument Altivec builtin functions.  */
 BU_ALTIVEC_1 (VEXPTEFP,              "vexptefp",       FP,     altivec_vexptefp)
 BU_ALTIVEC_1 (VLOGEFP,       "vlogefp",        FP,     altivec_vlogefp)
@@ -1420,6 +1428,7 @@ BU_ALTIVEC_OVERLOAD_1 (FLOOR,        "floor")
 BU_ALTIVEC_OVERLOAD_1 (LOGE,      "loge")
 BU_ALTIVEC_OVERLOAD_1 (MTVSCR,    "mtvscr")
 BU_ALTIVEC_OVERLOAD_1 (NEARBYINT,  "nearbyint")
+BU_ALTIVEC_OVERLOAD_1 (NEG,       "neg")
 BU_ALTIVEC_OVERLOAD_1 (RE,        "re")
 BU_ALTIVEC_OVERLOAD_1 (RINT,       "rint")
 BU_ALTIVEC_OVERLOAD_1 (ROUND,     "round")
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 80aab5f..3309f8d 100644 (file)
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2222,6 +2222,20 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
+
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V16QI,
+    RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V8HI,
+    RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SI,
+    RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DI,
+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SF,
+    RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DF,
+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
+
   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 1255995..f2b3042 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -16343,6 +16343,13 @@ vector signed int vec_nabs (vector signed int);
 vector float vec_nabs (vector float);
 vector double vec_nabs (vector double);
 
+vector signed char vec_neg (vector signed char);
+vector signed short vec_neg (vector signed short);
+vector signed int vec_neg (vector signed int);
+vector signed long long vec_neg (vector signed long long);
+vector float  char vec_neg (vector float);
+vector double vec_neg (vector double);
+
 vector float vec_nor (vector float, vector float);
 vector signed int vec_nor (vector signed int, vector signed int);
 vector unsigned int vec_nor (vector unsigned int, vector unsigned int);
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e300900..ef45039 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2017-05-10  Carl Love  <cel@us.ibm.com>
+       * gcc.target/powerpc/builtins-3.c: Add tests for the new built-ins to
+       to the test suite file.
+       * gcc.target/powerpc/builtins-3-p8.c: Add tests for the new built-ins to
+       to the test suite file.
+
 2017-05-10  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
 
        PR tree-optimization/77644
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
index 90e573d..629a692 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
@@ -36,18 +36,25 @@ test_vui_packs_vull_vull (vector unsigned long long x,
   return vec_packs (x, y);
 }
 
+vector long long
+test_neg_long_long (vector long long x)
+{
+       return vec_neg (x);
+}
+
 /* Expected test results:
 
      test_eq_long_long          1 vcmpequd inst
      test_pack_float            1 vpkudum inst
      test_nabs_long_long        1 vspltisw, 1 vsubudm, 1 vminsd
      test_vsi_packs_vsll_vsll   1 vpksdss
-     test_vui_packs_vull_vull   1 vpkudus */
+     test_vui_packs_vull_vull   1 vpkudus
+     test_neg_long_long         1 vspltisw, 1 vsubudm */
 
 /* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
 /* { dg-final { scan-assembler-times "vpkudum"  1 } } */
-/* { dg-final { scan-assembler-times "vspltisw" 1 } } */
-/* { dg-final { scan-assembler-times "vsubudm"  1 } } */
+/* { dg-final { scan-assembler-times "vspltisw" 2 } } */
+/* { dg-final { scan-assembler-times "vsubudm"  2 } } */
 /* { dg-final { scan-assembler-times "vminsd"   1 } } */
 /* { dg-final { scan-assembler-times "vpksdss"  1 } } */
 /* { dg-final { scan-assembler-times "vpkudus"  1 } } */  
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
index bddd0ac..5998c08 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
@@ -58,6 +58,36 @@ test_nabs_double (vector double x)
        return vec_nabs (x);
 }
 
+vector signed char
+test_neg_char (vector signed char x)
+{
+       return vec_neg (x);
+}
+
+vector short
+test_neg_short (vector short x)
+{
+       return vec_neg (x);
+}
+
+vector int
+test_neg_int (vector int x)
+{
+       return vec_neg (x);
+}
+
+vector float
+test_neg_float (vector float x)
+{
+       return vec_neg (x);
+}
+
+vector double
+test_neg_double (vector double x)
+{
+       return vec_neg (x);
+}
+
 /* Expected test results:
 
      test_eq_char              1 vcmpequb inst
@@ -68,19 +98,26 @@ test_nabs_double (vector double x)
      test_nabs_short           1 vspltisw, 1 vsubuhm, 1 vminsh
      test_nabs_int             1 vspltisw, 1 vsubuwm, 1 vminsw
      test_nabs_float           1 xvnabssp
-     test_nabs_double          1 xvnabsdp */
+     test_nabs_double          1 xvnabsdp
+     test_neg_char             1 vspltisw, 1 vsububm
+     test_neg_short            1 vspltisw, 1 vsubuhm
+     test_neg_int              1 vspltisw, 1 vsubuwm
+     test_neg_float            1 xvnegsp
+     test_neg_float            1 xvnegdp */
 
 /* { dg-final { scan-assembler-times "vcmpequb" 1 } } */
 /* { dg-final { scan-assembler-times "vcmpequh" 1 } } */
 /* { dg-final { scan-assembler-times "vcmpequw" 1 } } */
 /* { dg-final { scan-assembler-times "vsldoi"   1 } } */
-/* { dg-final { scan-assembler-times "vsububm"  1 } } */
-/* { dg-final { scan-assembler-times "vsubuhm"  1 } } */
-/* { dg-final { scan-assembler-times "vsubuwm"  1 } } */
+/* { dg-final { scan-assembler-times "vsububm"  2 } } */
+/* { dg-final { scan-assembler-times "vsubuhm"  2 } } */
+/* { dg-final { scan-assembler-times "vsubuwm"  2 } } */
 /* { dg-final { scan-assembler-times "vminsb"   1 } } */
 /* { dg-final { scan-assembler-times "vminsh"   1 } } */
 /* { dg-final { scan-assembler-times "vminsw"   1 } } */
-/* { dg-final { scan-assembler-times "vspltisw" 3 } } */
+/* { dg-final { scan-assembler-times "vspltisw" 6 } } */
 /* { dg-final { scan-assembler-times "xvnabssp" 1 } } */
 /* { dg-final { scan-assembler-times "xvnabsdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnegsp"  1 } } */
+/* { dg-final { scan-assembler-times "xvnegdp"  1 } } */
 
Domain: System / Toolchain;