raw_spinlock_t lock;
unsigned long irq_mask;
unsigned long flow_mask;
- unsigned base;
+ void __iomem *base;
};
static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
ws16c48gpio->io_state[port] |= mask;
ws16c48gpio->out_state[port] &= ~mask;
- outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
+ iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
ws16c48gpio->out_state[port] |= mask;
else
ws16c48gpio->out_state[port] &= ~mask;
- outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
+ iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
return -EINVAL;
}
- port_state = inb(ws16c48gpio->base + port);
+ port_state = ioread8(ws16c48gpio->base + port);
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
unsigned long offset;
unsigned long gpio_mask;
- unsigned int port_addr;
+ void __iomem *port_addr;
unsigned long port_state;
/* clear bits array to a clean slate */
for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
port_addr = ws16c48gpio->base + offset / 8;
- port_state = inb(port_addr) & gpio_mask;
+ port_state = ioread8(port_addr) & gpio_mask;
bitmap_set_value8(bits, port_state, offset);
}
ws16c48gpio->out_state[port] |= mask;
else
ws16c48gpio->out_state[port] &= ~mask;
- outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
+ iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}
unsigned long offset;
unsigned long gpio_mask;
size_t index;
- unsigned int port_addr;
+ void __iomem *port_addr;
unsigned long bitmask;
unsigned long flags;
/* update output state data and set device gpio register */
ws16c48gpio->out_state[index] &= ~gpio_mask;
ws16c48gpio->out_state[index] |= bitmask;
- outb(ws16c48gpio->out_state[index], port_addr);
+ iowrite8(ws16c48gpio->out_state[index], port_addr);
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}
port_state = ws16c48gpio->irq_mask >> (8*port);
- outb(0x80, ws16c48gpio->base + 7);
- outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
- outb(port_state | mask, ws16c48gpio->base + 8 + port);
- outb(0xC0, ws16c48gpio->base + 7);
+ iowrite8(0x80, ws16c48gpio->base + 7);
+ iowrite8(port_state & ~mask, ws16c48gpio->base + 8 + port);
+ iowrite8(port_state | mask, ws16c48gpio->base + 8 + port);
+ iowrite8(0xC0, ws16c48gpio->base + 7);
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}
ws16c48gpio->irq_mask &= ~mask;
- outb(0x80, ws16c48gpio->base + 7);
- outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
- outb(0xC0, ws16c48gpio->base + 7);
+ iowrite8(0x80, ws16c48gpio->base + 7);
+ iowrite8(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
+ iowrite8(0xC0, ws16c48gpio->base + 7);
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}
ws16c48gpio->irq_mask |= mask;
- outb(0x80, ws16c48gpio->base + 7);
- outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
- outb(0xC0, ws16c48gpio->base + 7);
+ iowrite8(0x80, ws16c48gpio->base + 7);
+ iowrite8(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
+ iowrite8(0xC0, ws16c48gpio->base + 7);
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}
return -EINVAL;
}
- outb(0x40, ws16c48gpio->base + 7);
- outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
- outb(0xC0, ws16c48gpio->base + 7);
+ iowrite8(0x40, ws16c48gpio->base + 7);
+ iowrite8(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
+ iowrite8(0xC0, ws16c48gpio->base + 7);
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
unsigned long int_id;
unsigned long gpio;
- int_pending = inb(ws16c48gpio->base + 6) & 0x7;
+ int_pending = ioread8(ws16c48gpio->base + 6) & 0x7;
if (!int_pending)
return IRQ_NONE;
/* loop until all pending interrupts are handled */
do {
for_each_set_bit(port, &int_pending, 3) {
- int_id = inb(ws16c48gpio->base + 8 + port);
+ int_id = ioread8(ws16c48gpio->base + 8 + port);
for_each_set_bit(gpio, &int_id, 8)
generic_handle_domain_irq(chip->irq.domain,
gpio + 8*port);
}
- int_pending = inb(ws16c48gpio->base + 6) & 0x7;
+ int_pending = ioread8(ws16c48gpio->base + 6) & 0x7;
} while (int_pending);
return IRQ_HANDLED;
struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
/* Disable IRQ by default */
- outb(0x80, ws16c48gpio->base + 7);
- outb(0, ws16c48gpio->base + 8);
- outb(0, ws16c48gpio->base + 9);
- outb(0, ws16c48gpio->base + 10);
- outb(0xC0, ws16c48gpio->base + 7);
+ iowrite8(0x80, ws16c48gpio->base + 7);
+ iowrite8(0, ws16c48gpio->base + 8);
+ iowrite8(0, ws16c48gpio->base + 9);
+ iowrite8(0, ws16c48gpio->base + 10);
+ iowrite8(0xC0, ws16c48gpio->base + 7);
return 0;
}
return -EBUSY;
}
+ ws16c48gpio->base = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
+ if (!ws16c48gpio->base)
+ return -ENOMEM;
+
ws16c48gpio->chip.label = name;
ws16c48gpio->chip.parent = dev;
ws16c48gpio->chip.owner = THIS_MODULE;
ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
ws16c48gpio->chip.set = ws16c48_gpio_set;
ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
- ws16c48gpio->base = base[id];
girq = &ws16c48gpio->chip.irq;
girq->chip = &ws16c48_irqchip;