arm64: dts: zynqmp: Wire up the DisplayPort subsystem
authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Thu, 21 Jan 2021 12:36:07 +0000 (13:36 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 1 Feb 2021 09:40:37 +0000 (10:40 +0100)
Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
the DisplayPort connector.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/9769d4d103b6eb75e3324825117f6832a746004e.1611232558.git.michal.simek@xilinx.com
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts

index 71ebcaa..a53598c 100644 (file)
@@ -15,6 +15,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
        model = "ZynqMP ZCU100 RevC";
                compatible = "iio-hwmon";
                io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
        };
+
+       si5335a_0: clk26 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <26000000>;
+       };
+
+       si5335a_1: clk27 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <27000000>;
+       };
 };
 
 &dcc {
        };
 };
 
+&psgtr {
+       status = "okay";
+       /* usb3, dps */
+       clocks = <&si5335a_0>, <&si5335a_1>;
+       clock-names = "ref0", "ref1";
+};
+
 &rtc {
        status = "okay";
 };
 &watchdog0 {
        status = "okay";
 };
+
+&zynqmp_dpdma {
+       status = "okay";
+};
+
+&zynqmp_dpsub {
+       status = "okay";
+       phy-names = "dp-phy0", "dp-phy1";
+       phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
+              <&psgtr 0 PHY_TYPE_DP 1 1>;
+};
index 9abd10f..12e8bd4 100644 (file)
 &watchdog0 {
        status = "okay";
 };
+
+&zynqmp_dpdma {
+       status = "okay";
+};
+
+&zynqmp_dpsub {
+       status = "okay";
+       phy-names = "dp-phy0";
+       phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
+};
index 8ede619..5637e1c 100644 (file)
 &watchdog0 {
        status = "okay";
 };
+
+&zynqmp_dpdma {
+       status = "okay";
+};
+
+&zynqmp_dpsub {
+       status = "okay";
+       phy-names = "dp-phy0", "dp-phy1";
+       phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+              <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
index 414f98f..7f2e328 100644 (file)
 &watchdog0 {
        status = "okay";
 };
+
+&zynqmp_dpdma {
+       status = "okay";
+};
+
+&zynqmp_dpsub {
+       status = "okay";
+       phy-names = "dp-phy0", "dp-phy1";
+       phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+              <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
index d60a307..18771e8 100644 (file)
        status = "okay";
 };
 
+&zynqmp_dpdma {
+       status = "okay";
+};
+
+&zynqmp_dpsub {
+       status = "okay";
+       phy-names = "dp-phy0", "dp-phy1";
+       phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+              <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
+
 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
        status = "okay";
index 758de05..d4b68f0 100644 (file)
        status = "okay";
        dr_mode = "host";
 };
+
+&zynqmp_dpdma {
+       status = "okay";
+};
+
+&zynqmp_dpsub {
+       status = "okay";
+       phy-names = "dp-phy0", "dp-phy1";
+       phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
+              <&psgtr 0 PHY_TYPE_DP 1 1>;
+};