gallium/radeon: remove stencil_tile_split from metadata
authorMarek Olšák <marek.olsak@amd.com>
Sun, 1 May 2016 13:47:30 +0000 (15:47 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 2 May 2016 20:49:25 +0000 (22:49 +0200)
this is a leftover from the days when depth-stencil buffers were
allocated by the DDX

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
src/gallium/drivers/radeon/r600_texture.c
src/gallium/drivers/radeon/radeon_winsys.h
src/gallium/winsys/radeon/drm/radeon_drm_bo.c

index 9aca0c2..67b2a34 100644 (file)
@@ -245,7 +245,6 @@ static void r600_texture_init_metadata(struct r600_texture *rtex,
        metadata->bankw = surface->bankw;
        metadata->bankh = surface->bankh;
        metadata->tile_split = surface->tile_split;
-       metadata->stencil_tile_split = surface->stencil_tile_split;
        metadata->mtilea = surface->mtilea;
        metadata->num_banks = surface->num_banks;
        metadata->stride = surface->level[0].pitch_bytes;
@@ -1035,7 +1034,6 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
        surface.bankw = metadata.bankw;
        surface.bankh = metadata.bankh;
        surface.tile_split = metadata.tile_split;
-       surface.stencil_tile_split = metadata.stencil_tile_split;
        surface.mtilea = metadata.mtilea;
        surface.num_banks = metadata.num_banks;
 
index 626f766..79c548c 100644 (file)
@@ -293,7 +293,6 @@ struct radeon_bo_metadata {
     unsigned                bankw;
     unsigned                bankh;
     unsigned                tile_split;
-    unsigned                stencil_tile_split;
     unsigned                mtilea;
     unsigned                num_banks;
     unsigned                stride;
index 2c3098e..dd41dc7 100644 (file)
@@ -665,7 +665,6 @@ static void radeon_bo_get_metadata(struct pb_buffer *_buf,
     md->bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
     md->bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
     md->tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
-    md->stencil_tile_split = (args.tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
     md->mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
     md->tile_split = eg_tile_split(md->tile_split);
     md->scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT);
@@ -698,9 +697,6 @@ static void radeon_bo_set_metadata(struct pb_buffer *_buf,
                              RADEON_TILING_EG_TILE_SPLIT_MASK) <<
            RADEON_TILING_EG_TILE_SPLIT_SHIFT;
     }
-    args.tiling_flags |= (md->stencil_tile_split &
-                         RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
-        RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
     args.tiling_flags |= (md->mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
         RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;