* internal.h (H8/300 specific relocs): Add comments better

        explaining what each reloc is used for.
        (R_MOV16B1, R_MOV16B2): Renamed from R_MOVB1 and R_MOVB2.
        (R_MOV24B1, R_MOV24B2): Renamed from R_MOVLB1 and R_MOVLB2.
        (R_MOVL1, R_MOVL2): New relocs.
More changes for the H8/300 relaxing linker.  HMSE.

diff --git a/include/coff/ChangeLog b/include/coff/ChangeLog
index 2b332a7..edb8de3 100644 (file)
--- a/include/coff/ChangeLog
+++ b/include/coff/ChangeLog
@@ -1,3 +1,11 @@
+Tue May  7 00:36:39 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * internal.h (H8/300 specific relocs): Add comments better
+       explaining what each reloc is used for.
+       (R_MOV16B1, R_MOV16B2): Renamed from R_MOVB1 and R_MOVB2.
+       (R_MOV24B1, R_MOV24B2): Renamed from R_MOVLB1 and R_MOVLB2.
+       (R_MOVL1, R_MOVL2): New relocs.
+       
 Fri May  3 13:01:12 1996  Jeffrey A Law  (law@cygnus.com)
 
        * internal.h (R_PCRWORD_B): Define for the h8300 relaxing

diff --git a/include/coff/internal.h b/include/coff/internal.h
index cc09d51..b414236 100644 (file)
--- a/include/coff/internal.h
+++ b/include/coff/internal.h
@@ -591,27 +591,65 @@ struct internal_reloc
 #define R_JUMPTARG     0x20    /* strange 29k 00xx00xx reloc */
 
 
-#define R_MOVB1        0x41    /* Special h8 16bit or 8 bit reloc for mov.b    */
-#define R_MOVB2        0x42    /* Special h8 opcode for 8bit which could be 16 */
-#define R_JMP1         0x43    /* Special h8 16bit jmp which could be pcrel    */
-#define R_JMP2                 0x44    /* a branch which used to be a jmp              */
+/* This reloc identifies mov.b instructions with a 16bit absolute
+   address.  The linker tries to turn insns with this reloc into
+   an absolute 8-bit address.  */
+#define R_MOV16B1      0x41
+
+/* This reloc identifies mov.b instructions which had a 16bit
+   absolute address which have been shortened into a 8-bit
+   absolute address.  */
+#define R_MOV16B2      0x42
+
+/* This reloc identifies jmp insns with a 16bit target address;
+   the linker tries to turn these insns into bra insns with
+   an 8bit pc-relative target.  */
+#define R_JMP1         0x43
+
+/* This reloc identifies a bra with an 8-bit pc-relative
+   target that was formerlly a jmp insn with a 16bit target.  */
+#define R_JMP2                 0x44
+
+/* ??? */
 #define R_RELLONG_NEG          0x45
 
-#define R_JMPL1        0x46    /* Special h8 24bit jmp which could be pcrel    */
-#define R_JMPL_B8      0x47    /* a 8 bit pcrel which used to be a jmp  */
+/* This reloc identifies jmp insns with a 24bit target address;
+   the linker tries to turn these insns into bra insns with
+   an 8bit pc-relative target.  */
+#define R_JMPL1        0x46
 
-#define R_MOVLB1       0x48    /* Special h8 24bit or 8 bit reloc for mov.b    */
-#define R_MOVLB2       0x49    /* Special h8 opcode for 8bit which could be 24 */
+/* This reloc identifies a bra with an 8-bit pc-relative
+   target that was formerlly a jmp insn with a 24bit target.  */
+#define R_JMPL_B8      0x47
+
+/* This reloc identifies mov.b instructions with a 24bit absolute
+   address.  The linker tries to turn insns with this reloc into
+   an absolute 8-bit address.  */
+
+#define R_MOV24B1      0x48
+
+/* This reloc identifies mov.b instructions which had a 24bit
+   absolute address which have been shortened into a 8-bit
+   absolute address.  */
+#define R_MOV24B2      0x49
 
 /* An h8300 memory indirect jump/call.  Forces the address of the jump/call
    target into the function vector (in page zero), and the address of the
    vector entry to be placed in the jump/call instruction.  */
 #define R_MEM_INDIRECT 0x4a
 
-/* An h8300 special reloc for relaxing a 16bit pc-relative branch into
-   an 8bit pc-relative branch.  */
+/* This reloc identifies a 16bit pc-relative branch target which was
+   shortened into an 8bit pc-relative branch target.  */
 #define R_PCRWORD_B    0x4b
 
+/* This reloc identifies mov.[wl] instructions with a 32/24 bit
+   absolute address; the linker may turn this into a mov.[wl]
+   insn with a 16bit absolute address.  */
+#define R_MOVL1        0x4c
+
+/* This reloc identifies mov.[wl] insns which formerlly had
+   a 32/24bit absolute address and how have a 16bit absolute address.  */
+#define R_MOVL2        0x4d
 
 /* Z8k modes */
 #define R_IMM16   0x01         /* 16 bit abs */