intel: Add the Gen6+ version of MI_REPORT_PERF_COUNT to intel_decode.c.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index ff19f92..5bf0aff 100644 (file)
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -257,6 +257,7 @@ decode_mi(struct drm_intel_decode *ctx)
                { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT", decode_MI_WAIT_FOR_EVENT },
                { 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" },
                { 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" },
+               { 0x28, 0x3f, 3, 3, "MI_REPORT_PERF_COUNT" },
                { 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH"},
        }, *opcode_mi = NULL;