CCVal = ISD::getSetCCInverse(CCVal, SetCCOpVT);
NewLHS =
DAG.getSetCC(SDLoc(N1), VT, N1.getOperand(0), N1.getOperand(1), CCVal);
+ } else if (N1.getOpcode() == ISD::XOR && isOneConstant(N1.getOperand(1)) &&
+ N1.getOperand(0).getOpcode() == ISD::SETCC) {
+ // (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
+ // Since setcc returns a bool the xor is equivalent to 1-setcc.
+ NewLHS = N1.getOperand(0);
} else
return SDValue();
; CHECK-LABEL: select_fcmp_uge_negone_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.d a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: ret
%1 = fcmp ugt double %a, %b
%2 = select i1 %1, i32 -1, i32 0
; CHECK-LABEL: select_fcmp_uge_1_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.d a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: li a1, 2
-; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp ugt double %a, %b
%2 = select i1 %1, i32 1, i32 2
; CHECK-LABEL: select_fcmp_uge_negone_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.s a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: ret
%1 = fcmp ugt float %a, %b
%2 = select i1 %1, i32 -1, i32 0
; CHECK-LABEL: select_fcmp_uge_1_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.s a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: li a1, 2
-; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp ugt float %a, %b
%2 = select i1 %1, i32 1, i32 2
; CHECK-LABEL: select_fcmp_uge_negone_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.h a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: ret
%1 = fcmp ugt half %a, %b
%2 = select i1 %1, i32 -1, i32 0
; CHECK-LABEL: select_fcmp_uge_1_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.h a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: li a1, 2
-; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp ugt half %a, %b
%2 = select i1 %1, i32 1, i32 2