MDIO_PHY(phy_id));
while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
cpu_relax();
+
return MDIO_DATA(val);
}
cpu_relax();
cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
+
return 0;
}
ar7_device_reset(AR7_RESET_BIT_MDIO);
cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
+
return 0;
}
cpmac_hw_stop(priv->dev);
if (!schedule_work(&priv->reset_work))
atomic_dec(&priv->reset_pending);
+
return 0;
}
if (netif_running(dev))
return -EBUSY;
priv->ring_size = ring->rx_pending;
+
return 0;
}
dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
(CPMAC_QUEUES + priv->ring_size),
priv->desc_ring, priv->dma_ring);
+
return 0;
}
"mac: %pM\n", (void *)mem->start, dev->irq,
priv->phy_name, dev->dev_addr);
}
+
return 0;
fail:
unregister_netdev(dev);
free_netdev(dev);
+
return 0;
}