drm/amdgpu: add apu flags (v2)
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 15 May 2020 18:18:29 +0000 (14:18 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 22 May 2020 17:41:53 +0000 (13:41 -0400)
Add some APU flags to simplify handling of different APU
variants.  It's easier to understand the special cases
if we use names flags rather than checking device ids and
silicon revisions.

v2: rebase on latest code

Acked-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
15 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/include/amd_shared.h
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c

index 4922a2a6abb23d066ed00a424dfe3d49a4387c1d..cd913986863edc4ddeee45f1aa7f8b7dd7c7913d 100644 (file)
@@ -739,6 +739,7 @@ struct amdgpu_device {
        uint32_t                        rev_id;
        uint32_t                        external_rev_id;
        unsigned long                   flags;
+       unsigned long                   apu_flags;
        int                             usec_timeout;
        const struct amdgpu_asic_funcs  *asic_funcs;
        bool                            shutdown;
index d46b400cb67fb1393c8957f649516d42a787a017..a027a8f7b28193c443788a1fec0f99acae702b69 100644 (file)
@@ -1567,9 +1567,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
                chip_name = "vega12";
                break;
        case CHIP_RAVEN:
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        chip_name = "raven2";
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        chip_name = "picasso";
                else
                        chip_name = "raven";
index 84cee27cd7efb4c4b05b40f099cc2ef117c29ec0..f7143d927b6d8126c7fc445e29eb57e2cfa53fb4 100644 (file)
@@ -523,7 +523,8 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
                        break;
                case CHIP_RAVEN:
                        /* enable S/G on PCO and RV2 */
-                       if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
+                       if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
+                           (adev->apu_flags & AMD_APU_IS_PICASSO))
                                domain |= AMDGPU_GEM_DOMAIN_GTT;
                        break;
                default:
index 655f0d3fb1e40d6477e8a469190aaef6b9e4242d..702a3a03c707d029e47782e443c57ae2d12826a4 100644 (file)
@@ -372,7 +372,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
        }
 
        if (adev->asic_type == CHIP_RAVEN) {
-               if (adev->rev_id < 8) {
+               if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
                        if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
                                amdgpu_gfx_off_ctrl(adev, false);
                        else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
index 2de99b4416018c3bbc8d33a57e9c0e8dc47ce89d..2badbc0355f204d1db7a1efb91766452b831e67a 100644 (file)
@@ -70,9 +70,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_RAVEN:
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        fw_name = FIRMWARE_RAVEN2;
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        fw_name = FIRMWARE_PICASSO;
                else
                        fw_name = FIRMWARE_RAVEN;
index 1573ac1f03b246d999629549a7af64b51371324f..711e9dd1970555beb79c47f688ad9dea7b5b5d56 100644 (file)
@@ -959,7 +959,7 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_RAVEN:
                soc15_program_register_sequence(adev, golden_settings_gc_9_1,
                                                ARRAY_SIZE(golden_settings_gc_9_1));
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        soc15_program_register_sequence(adev,
                                                        golden_settings_gc_9_1_rv2,
                                                        ARRAY_SIZE(golden_settings_gc_9_1_rv2));
@@ -1274,7 +1274,8 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
        case CHIP_VEGA20:
                break;
        case CHIP_RAVEN:
-               if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) &&
+               if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
+                     (adev->apu_flags & AMD_APU_IS_PICASSO)) &&
                    ((!is_raven_kicker(adev) &&
                      adev->gfx.rlc_fw_version < 531) ||
                     (adev->gfx.rlc_feature_version < 1) ||
@@ -1617,9 +1618,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
                chip_name = "vega20";
                break;
        case CHIP_RAVEN:
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        chip_name = "raven2";
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        chip_name = "picasso";
                else
                        chip_name = "raven";
@@ -2119,7 +2120,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
                else
                        gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
@@ -2968,8 +2969,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
         */
        if (adev->gfx.rlc.is_rlc_v2_1) {
                if (adev->asic_type == CHIP_VEGA12 ||
-                   (adev->asic_type == CHIP_RAVEN &&
-                    adev->rev_id >= 8))
+                   (adev->apu_flags & AMD_APU_IS_RAVEN2))
                        gfx_v9_1_init_rlc_save_restore_list(adev);
                gfx_v9_0_enable_save_restore_machine(adev);
        }
@@ -6881,7 +6881,7 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
                adev->gds.gds_compute_max_wave_id = 0x27f;
                break;
        case CHIP_RAVEN:
-               if (adev->rev_id >= 0x8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */
                else
                        adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
index 1a2f18b908fee4040a3e4c93953331ca6c3ead14..6682b843bafe467ac3a4c87bc87a6bb73b197d30 100644 (file)
@@ -80,7 +80,7 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
                WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
                        min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 
-               if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        /*
                        * Raven2 has a HW issue that it is unable to use the
                        * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
index 055ecba754fff8b7f41700a76daef57102e2ba3b..11e93a82131def7ee7f231d1f29b06e81cddaaf4 100644 (file)
@@ -441,9 +441,8 @@ static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
        return ((vmhub == AMDGPU_MMHUB_0 ||
                 vmhub == AMDGPU_MMHUB_1) &&
                (!amdgpu_sriov_vf(adev)) &&
-               (!(adev->asic_type == CHIP_RAVEN &&
-                  adev->rev_id < 0x8 &&
-                  adev->pdev->device == 0x15d8)));
+               (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
+                  (adev->apu_flags & AMD_APU_IS_PICASSO))));
 }
 
 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
index bd2d2b8d1f429092e54d02c231b738dd84cd98ab..405767208a4d1be56e6474ecfb16ea8fcdd00236 100755 (executable)
@@ -96,7 +96,7 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
        WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
                     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 
-       if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
+       if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                /*
                 * Raven2 has a HW issue that it is unable to use the vram which
                 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
index 90727cfb4447fe30a53afcc6ce2131ef61bf98d9..d7f92634eba271e40e5c1e219dfbb28a563a0bbb 100644 (file)
@@ -55,9 +55,9 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
 
        switch (adev->asic_type) {
        case CHIP_RAVEN:
-               if (adev->rev_id >= 0x8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        chip_name = "raven2";
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        chip_name = "picasso";
                else
                        chip_name = "raven";
index ebd723a0bcfced12ea9d5e9beb2ecd744e6eb775..33501c6c71895e8ee33e8282bfe2cc2555050ec2 100644 (file)
@@ -486,7 +486,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
                soc15_program_register_sequence(adev,
                                                golden_settings_sdma_4_1,
                                                ARRAY_SIZE(golden_settings_sdma_4_1));
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        soc15_program_register_sequence(adev,
                                                        golden_settings_sdma_rv2,
                                                        ARRAY_SIZE(golden_settings_sdma_rv2));
@@ -575,9 +575,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
                chip_name = "vega20";
                break;
        case CHIP_RAVEN:
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        chip_name = "raven2";
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        chip_name = "picasso";
                else
                        chip_name = "raven";
index 58a440a15525a932d9f4bfddb167fabee407903d..c7c9e07962b96ee312a49de04dd96ccd363de3a2 100644 (file)
@@ -564,7 +564,8 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
 static int soc15_asic_reset(struct amdgpu_device *adev)
 {
        /* original raven doesn't have full asic reset */
-       if (adev->pdev->device == 0x15dd && adev->rev_id < 0x8)
+       if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
+           !(adev->apu_flags & AMD_APU_IS_RAVEN2))
                return 0;
 
        switch (soc15_asic_reset_method(adev)) {
@@ -1129,16 +1130,23 @@ static int soc15_common_early_init(void *handle)
                break;
        case CHIP_RAVEN:
                adev->asic_funcs = &soc15_asic_funcs;
+               if (adev->pdev->device == 0x15dd)
+                       adev->apu_flags |= AMD_APU_IS_RAVEN;
+               if (adev->pdev->device == 0x15d8)
+                       adev->apu_flags |= AMD_APU_IS_PICASSO;
                if (adev->rev_id >= 0x8)
+                       adev->apu_flags |= AMD_APU_IS_RAVEN2;
+
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        adev->external_rev_id = adev->rev_id + 0x79;
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        adev->external_rev_id = adev->rev_id + 0x41;
                else if (adev->rev_id == 1)
                        adev->external_rev_id = adev->rev_id + 0x20;
                else
                        adev->external_rev_id = adev->rev_id + 0x01;
 
-               if (adev->rev_id >= 0x8) {
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
                        adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                                AMD_CG_SUPPORT_GFX_MGLS |
                                AMD_CG_SUPPORT_GFX_CP_LS |
@@ -1156,7 +1164,7 @@ static int soc15_common_early_init(void *handle)
                                AMD_CG_SUPPORT_VCN_MGCG;
 
                        adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
-               } else if (adev->pdev->device == 0x15d8) {
+               } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
                        adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                                AMD_CG_SUPPORT_GFX_MGLS |
                                AMD_CG_SUPPORT_GFX_CP_LS |
@@ -1222,6 +1230,7 @@ static int soc15_common_early_init(void *handle)
                break;
        case CHIP_RENOIR:
                adev->asic_funcs = &soc15_asic_funcs;
+               adev->apu_flags |= AMD_APU_IS_RENOIR;
                adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                                 AMD_CG_SUPPORT_GFX_MGLS |
                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
index 92126c54cb1ce3b53477e6268d43d57fe4fd4348..e98c84ef206fec4a4a54c21d8a18fc1d0480e454 100644 (file)
@@ -40,6 +40,13 @@ enum amd_chip_flags {
        AMD_EXP_HW_SUPPORT = 0x00080000UL,
 };
 
+enum amd_apu_flags {
+       AMD_APU_IS_RAVEN = 0x00000001UL,
+       AMD_APU_IS_RAVEN2 = 0x00000002UL,
+       AMD_APU_IS_PICASSO = 0x00000004UL,
+       AMD_APU_IS_RENOIR = 0x00000008UL,
+};
+
 enum amd_ip_block_type {
        AMD_IP_BLOCK_TYPE_COMMON,
        AMD_IP_BLOCK_TYPE_GMC,
index d1f0cc77d460360a02636ee58ef7170707577545..c9cfe90a29471c6590b34b228711ae98c5e06658 100644 (file)
@@ -1302,8 +1302,7 @@ static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
 {
        struct amdgpu_device *adev = hwmgr->adev;
-       if ((adev->asic_type == CHIP_RAVEN) &&
-           (adev->rev_id != 0x15d8) &&
+       if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
            (hwmgr->smu_version >= 0x41e2b))
                return true;
        else
index 801ba9ca6094381603c22f5c03f2e80ee9cbfb21..ea2279bb8cbfd24a77799e9ee5acb0896b347ef8 100644 (file)
@@ -226,7 +226,8 @@ static int smu10_start_smu(struct pp_hwmgr *hwmgr)
        smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version);
        adev->pm.fw_version = hwmgr->smu_version >> 8;
 
-       if (adev->rev_id < 0x8 && adev->pdev->device != 0x15d8 &&
+       if (!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
+           (adev->apu_flags & AMD_APU_IS_RAVEN) &&
            adev->pm.fw_version < 0x1e45)
                adev->pm.pp_feature &= ~PP_GFXOFF_MASK;