PPC4xx: Denali core: Fix incorrect DDR row bits

The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.

Signed-off-by: Mike Nuss <mike@terascala.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index 4705e21..5858cb3 100644 (file)
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -1159,7 +1159,7 @@ phys_size_t initdram(int board_type)
 
        mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
 
-       mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) |
+       mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) |
                DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
 
        program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,