drm/i915: Make display gtt offsets u32

Using 'unsigned long' for ggtt offsets doesn't make much sense. Use
'u32' instead since we've not yet seen a >4GiB ggtt.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453316739-13296-5-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f54e119..97af94a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2448,11 +2448,11 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
 
 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  * is assumed to be a power-of-two. */
-unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
-                                       int *x, int *y,
-                                       uint64_t fb_modifier,
-                                       unsigned int cpp,
-                                       unsigned int pitch)
+u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
+                             int *x, int *y,
+                             uint64_t fb_modifier,
+                             unsigned int cpp,
+                             unsigned int pitch)
 {
        if (fb_modifier != DRM_FORMAT_MOD_NONE) {
                unsigned int tile_size, tile_width, tile_height;
@@ -2706,14 +2706,12 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
        struct drm_framebuffer *fb = plane_state->base.fb;
        struct drm_i915_gem_object *obj = intel_fb_obj(fb);
        int plane = intel_crtc->plane;
-       unsigned long linear_offset;
-       int x = plane_state->src.x1 >> 16;
-       int y = plane_state->src.y1 >> 16;
+       u32 linear_offset;
        u32 dspcntr;
        i915_reg_t reg = DSPCNTR(plane);
-       int pixel_size;
-
-       pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+       int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+       int x = plane_state->src.x1 >> 16;
+       int y = plane_state->src.y1 >> 16;
 
        dspcntr = DISPPLANE_GAMMA_ENABLE;
 
@@ -2839,7 +2837,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
        struct drm_framebuffer *fb = plane_state->base.fb;
        struct drm_i915_gem_object *obj = intel_fb_obj(fb);
        int plane = intel_crtc->plane;
-       unsigned long linear_offset;
+       u32 linear_offset;
        u32 dspcntr;
        i915_reg_t reg = DSPCNTR(plane);
        int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bc97012..f620023 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -575,7 +575,7 @@ struct intel_crtc {
        /* Display surface base address adjustement for pageflips. Note that on
         * gen4+ this only adjusts up to a tile, offsets within a tile are
         * handled in the hw itself (with the TILEOFF register). */
-       unsigned long dspaddr_offset;
+       u32 dspaddr_offset;
        int adjusted_x;
        int adjusted_y;
 
@@ -1172,11 +1172,11 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
-unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
-                                       int *x, int *y,
-                                       uint64_t fb_modifier,
-                                       unsigned int cpp,
-                                       unsigned int pitch);
+u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
+                             int *x, int *y,
+                             uint64_t fb_modifier,
+                             unsigned int cpp,
+                             unsigned int pitch);
 void intel_prepare_reset(struct drm_device *dev);
 void intel_finish_reset(struct drm_device *dev);
 void hsw_enable_pc8(struct drm_i915_private *dev_priv);

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0875c8e..f1ee7db 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -350,7 +350,7 @@ vlv_update_plane(struct drm_plane *dplane,
        int pipe = intel_plane->pipe;
        int plane = intel_plane->plane;
        u32 sprctl;
-       unsigned long sprsurf_offset, linear_offset;
+       u32 sprsurf_offset, linear_offset;
        int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
        const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
        int crtc_x = plane_state->dst.x1;
@@ -493,7 +493,7 @@ ivb_update_plane(struct drm_plane *plane,
        struct drm_i915_gem_object *obj = intel_fb_obj(fb);
        enum pipe pipe = intel_plane->pipe;
        u32 sprctl, sprscale = 0;
-       unsigned long sprsurf_offset, linear_offset;
+       u32 sprsurf_offset, linear_offset;
        int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
        const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
        int crtc_x = plane_state->dst.x1;
@@ -635,8 +635,8 @@ ilk_update_plane(struct drm_plane *plane,
        struct drm_framebuffer *fb = plane_state->base.fb;
        struct drm_i915_gem_object *obj = intel_fb_obj(fb);
        int pipe = intel_plane->pipe;
-       unsigned long dvssurf_offset, linear_offset;
        u32 dvscntr, dvsscale;
+       u32 dvssurf_offset, linear_offset;
        int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
        const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
        int crtc_x = plane_state->dst.x1;