drm/amd/display: Fix DCN2.1 default DSC clocks

[WHY]
Low dscclk in high vlevels blocks some DSC modes.

[HOW]
Update dscclk to 1/3 of dispclk.

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index c4eca10..c26da3b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -565,7 +565,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
                                .dppclk_mhz = 847.06,
                                .phyclk_mhz = 810.0,
                                .socclk_mhz = 953.0,
-                               .dscclk_mhz = 489.0,
+                               .dscclk_mhz = 300.0,
                                .dram_speed_mts = 2400.0,
                        },
                        {
@@ -576,7 +576,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
                                .dppclk_mhz = 960.00,
                                .phyclk_mhz = 810.0,
                                .socclk_mhz = 278.0,
-                               .dscclk_mhz = 287.67,
+                               .dscclk_mhz = 342.86,
                                .dram_speed_mts = 2666.0,
                        },
                        {
@@ -587,7 +587,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
                                .dppclk_mhz = 1028.57,
                                .phyclk_mhz = 810.0,
                                .socclk_mhz = 715.0,
-                               .dscclk_mhz = 318.334,
+                               .dscclk_mhz = 369.23,
                                .dram_speed_mts = 3200.0,
                        },
                        {