drm/amd/display: enable dsc_clk even if dsc_pg disabled

[ Upstream commit 40255df370e94d44f0f0a924400d68db0ee31bec ]

[why]
need to enable dsc_clk regardless dsc_pg

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 38abbd0..186936a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1843,7 +1843,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
        if (dc->hwss.subvp_pipe_control_lock)
                dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);
 
-       if (dc->debug.enable_double_buffered_dsc_pg_support)
+       if (dc->hwss.update_dsc_pg)
                dc->hwss.update_dsc_pg(dc, context, false);
 
        disable_dangling_plane(dc, context);
@@ -1950,7 +1950,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
                dc->hwss.optimize_bandwidth(dc, context);
        }
 
-       if (dc->debug.enable_double_buffered_dsc_pg_support)
+       if (dc->hwss.update_dsc_pg)
                dc->hwss.update_dsc_pg(dc, context, true);
 
        if (dc->ctx->dce_version >= DCE_VERSION_MAX)
@@ -2197,7 +2197,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
 
                dc->hwss.optimize_bandwidth(dc, context);
 
-               if (dc->debug.enable_double_buffered_dsc_pg_support)
+               if (dc->hwss.update_dsc_pg)
                        dc->hwss.update_dsc_pg(dc, context, true);
        }
 
@@ -3533,7 +3533,7 @@ static void commit_planes_for_stream(struct dc *dc,
                if (get_seamless_boot_stream_count(context) == 0)
                        dc->hwss.prepare_bandwidth(dc, context);
 
-               if (dc->debug.enable_double_buffered_dsc_pg_support)
+               if (dc->hwss.update_dsc_pg)
                        dc->hwss.update_dsc_pg(dc, context, false);
 
                context_clock_trace(dc, context);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index be59e1c..c9140b5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -77,6 +77,9 @@ void dcn32_dsc_pg_control(
        if (hws->ctx->dc->debug.disable_dsc_power_gate)
                return;
 
+       if (!hws->ctx->dc->debug.enable_double_buffered_dsc_pg_support)
+               return;
+
        REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
        if (org_ip_request_cntl == 0)
                REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);