uint32_t *sizes,
unsigned num_vbs)
{
+#if GFX_VER == 9
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
for (unsigned i = 0; i < num_vbs; i++) {
*/
genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(cmd_buffer, SEQUENTIAL,
(1 << num_vbs) - 1);
+#endif
}
UNUSED static struct blorp_address
.BufferSize = size
});
+#if GFX_VER == 9
genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer,
index, addr, size);
+#endif
}
static void
update_dirty_vbs_for_gfx8_vb_flush(struct anv_cmd_buffer *cmd_buffer,
uint32_t access_type)
{
+#if GFX_VER == 9
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(cmd_buffer,
access_type == RANDOM,
vb_used);
+#endif
}
ALWAYS_INLINE static void
#endif
}
+#if GFX_VER == 9
/* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
*
* "The VF cache needs to be invalidated before binding and then using
uint32_t access_type,
uint64_t vb_used)
{
- if (GFX_VER > 9)
- return;
-
if (access_type == RANDOM) {
/* We have an index buffer */
struct anv_vb_cache_range *bound = &cmd_buffer->state.gfx.ib_bound_range;
}
}
}
+#endif /* GFX_VER == 9 */
/**
* Update the pixel hashing modes that determine the balancing of PS threads
genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
}
+#if GFX_VER == 9
genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, 32, src, size);
+#endif
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
genX(flush_pipeline_select_3d)(cmd_buffer);
cmd_buffer->state.current_l3_config);
emit_so_memcpy(&cmd_buffer->batch, cmd_buffer->device, dst, src, size);
+#if GFX_VER == 9
genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(cmd_buffer, SEQUENTIAL,
1ull << 32);
+#endif
/* Invalidate pipeline & raster discard since we touch
* 3DSTATE_STREAMOUT.