RDMA/mlx5: Expose TIR and QP ICM address for sw_owner_v2 devices

Expose the ICM address to access TIR and QP, this will allow sw_owned_v2
devices to steer traffic to TIRs and QPs same as done with sw_owner
capability.

Link: https://lore.kernel.org/r/20200903073857.1129166-4-leon@kernel.org
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c
index 5758dbe..12f9f4b 100644 (file)
--- a/drivers/infiniband/hw/mlx5/qp.c
+++ b/drivers/infiniband/hw/mlx5/qp.c
@@ -1477,7 +1477,8 @@ static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
                        resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
                        resp->tirn = rq->tirn;
                        resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
-                       if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
+                       if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
+                           MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) {
                                resp->tir_icm_addr = MLX5_GET(
                                        create_tir_out, out, icm_address_31_0);
                                resp->tir_icm_addr |=
@@ -1739,7 +1740,8 @@ create_tir:
        if (mucontext->devx_uid) {
                params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
                params->resp.tirn = qp->rss_qp.tirn;
-               if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
+               if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
+                   MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) {
                        params->resp.tir_icm_addr =
                                MLX5_GET(create_tir_out, out, icm_address_31_0);
                        params->resp.tir_icm_addr |=