hdmirx: optimize recovery method for no signal issue
authorHang Cheng <hang.cheng@amlogic.com>
Wed, 30 May 2018 06:11:46 +0000 (14:11 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Wed, 6 Jun 2018 10:24:32 +0000 (03:24 -0700)
PD#167228: hdmirx: optimize recovery method for no signal issue

1.phy reset for no signal issue after esd test
2.run eq constantly if tmds can't lock

Change-Id: I1a4ad17459d1cdbb2e64f9d51830de9e0fffdb93
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_eq.c
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c

index b5ec1e2fa5e0397ea64e6b69d035dc39e6a2290c..a54535ec22f7239a251db86b4db5773d0f7ce5cc 100644 (file)
@@ -41,7 +41,7 @@
  *
  *
  */
-#define RX_VER1 "ver.2018/05/11"
+#define RX_VER1 "ver.2018/05/30"
 
 
 
index 901afd5ea3b8f7d0e0d9b65abab927c0f6cc3ee0..fa79e8d7fc19e8d41ce15eddd5233205b3e856ca 100644 (file)
@@ -185,6 +185,7 @@ void eq_dwork_handler(struct work_struct *work)
                        if (eq_maxvsmin(eq_ch0.bestsetting,
                                        eq_ch1.bestsetting,
                                        eq_ch2.bestsetting) == 1) {
+                               eq_sts = E_EQ_PASS;
                                if (log_level & EQ_LOG)
                                        rx_pr("pass\n");
                                break;
@@ -199,9 +200,9 @@ void eq_dwork_handler(struct work_struct *work)
                eq_ch2.bestsetting = ErrorcableSetting;
                if (log_level & EQ_LOG)
                        rx_pr("EQ fail-retry\n");
+               eq_sts = E_EQ_FAIL;
        }
        eq_cfg();
-       eq_sts = E_EQ_FINISH;
        /*rx_set_eq_run_state(E_EQ_FINISH);*/
        /*return;*/
 }
@@ -488,13 +489,14 @@ int rx_eq_algorithm(void)
                return 0;
        }
        if (pre_eq_freq == pll_rate) {
-               if ((eq_sts == E_EQ_FINISH) ||
+               if ((eq_sts == E_EQ_PASS) ||
                        (eq_sts == E_EQ_SAME)) {
                        eq_sts = E_EQ_SAME;
                        rx_pr("same pll rate\n");
                        return 0;
                }
-       } else if ((pll_rate&0x2) == E_EQ_SD) {
+       }
+       if ((pll_rate&0x2) == E_EQ_SD) {
                eq_sts = E_EQ_FINISH;
                pre_eq_freq = pll_rate;
                rx_pr("low pll rate\n");
index 4d4d2f0371e2e94067814065350664c78b658a87..33cf22de9b9b86cacaa56b6d2c674c9531cfd767 100644 (file)
@@ -198,6 +198,12 @@ int pre_port = 0xff;
 /*for some device pll unlock too long,send a hpd reset*/
 bool hdmi5v_lost_flag;
 static int hdcp_none_wait_max = 100;
+/* for no signal after esd test issue, phy
+ * does't work, cable clock or PLL can't
+ * lock, need to do phy reset.
+ */
+static int esd_phy_rst_cnt;
+static int esd_phy_rst_max = 2;
 
 #ifndef USE_NEW_FSM_METHODE
 int pll_unlock_check_times;
@@ -1642,6 +1648,10 @@ int rx_set_global_variable(const char *buf, int size)
                return pr_var(aud_ch_map, index);
        if (set_pr_var(tmpbuf, hdcp_none_wait_max, value, &index, ret))
                return pr_var(hdcp_none_wait_max, index);
+       if (set_pr_var(tmpbuf, pll_unlock_max, value, &index, ret))
+               return pr_var(pll_unlock_max, index);
+       if (set_pr_var(tmpbuf, esd_phy_rst_max, value, &index, ret))
+               return pr_var(esd_phy_rst_max, index);
        return 0;
 }
 
@@ -1742,6 +1752,8 @@ void rx_get_global_variable(const char *buf)
        pr_var(suspend_pddq_sel, i++);
        pr_var(aud_ch_map, i++);
        pr_var(hdcp_none_wait_max, i++);
+       pr_var(pll_unlock_max, i++);
+       pr_var(esd_phy_rst_max, i++);
 }
 
 void skip_frame(unsigned int cnt)
@@ -1965,10 +1977,11 @@ void rx_main_state_machine(void)
                }
                hpd_wait_cnt = 0;
                clk_unstable_cnt = 0;
+               esd_phy_rst_cnt = 0;
                pre_port = rx.port;
                rx_set_hpd(1);
                set_scdc_cfg(0, 1);
-               //rx.hdcp.hdcp_version = HDCP_VER_NONE;
+               /* rx.hdcp.hdcp_version = HDCP_VER_NONE; */
                rx.state = FSM_WAIT_CLK_STABLE;
                break;
        case FSM_WAIT_CLK_STABLE:
@@ -1985,12 +1998,17 @@ void rx_main_state_machine(void)
                                clk_unstable_cnt++;
                                break;
                        }
-                       if (rx.err_rec_mode != ERR_REC_END) {
-                               rx_set_hpd(0);
-                               rx.state = FSM_HPD_HIGH;
-                               rx.err_rec_mode = ERR_REC_END;
-                       } else
-                               rx.err_code = ERR_CLK_UNSTABLE;
+                       clk_unstable_cnt = 0;
+                       /* do phy reset for ESD no signal issue.
+                        * sometimes after phy reset, phy is
+                        * still not work, need to do phy reset
+                        * again. do reset twice at most.
+                        */
+                       if (esd_phy_rst_cnt < esd_phy_rst_max) {
+                               hdmirx_phy_init();
+                               esd_phy_rst_cnt++;
+                       }
+                       rx.err_code = ERR_CLK_UNSTABLE;
                }
                break;
        case FSM_EQ_START:
@@ -1998,8 +2016,7 @@ void rx_main_state_machine(void)
                rx.state = FSM_WAIT_EQ_DONE;
                break;
        case FSM_WAIT_EQ_DONE:
-               if ((rx_get_eq_run_state() == E_EQ_FINISH) ||
-                       (rx_get_eq_run_state() == E_EQ_SAME)) {
+               if (rx_get_eq_run_state() != E_EQ_START) {
                        rx.state = FSM_SIG_UNSTABLE;
                        pll_lock_cnt = 0;
                        pll_unlock_cnt = 0;
@@ -2021,14 +2038,22 @@ void rx_main_state_machine(void)
                        }
                        if (rx.err_rec_mode == ERR_REC_EQ_RETRY) {
                                rx.state = FSM_WAIT_CLK_STABLE;
-                               rx.err_rec_mode = ERR_REC_HPD_RST;
-                               rx_set_eq_run_state(E_EQ_START);
+                               /* pll unlock after ESD test, phy does't
+                                * work well, do phy reset twice at most.
+                                */
+                               if (esd_phy_rst_cnt++ < esd_phy_rst_max)
+                                       hdmirx_phy_init();
+                               else
+                                       rx.err_rec_mode = ERR_REC_HPD_RST;
                        } else if (rx.err_rec_mode == ERR_REC_HPD_RST) {
                                rx_set_hpd(0);
                                rx.state = FSM_HPD_HIGH;
                                rx.err_rec_mode = ERR_REC_END;
-                       } else
+                       } else {
+                               rx.state = FSM_WAIT_CLK_STABLE;
                                rx.err_code = ERR_PHY_UNLOCK;
+                       }
+                       rx_set_eq_run_state(E_EQ_START);
                }
                break;
        case FSM_SIG_WAIT_STABLE:
@@ -2110,6 +2135,7 @@ void rx_main_state_machine(void)
                break;
        case FSM_SIG_READY:
                rx_get_video_info();
+               rx.err_rec_mode = ERR_REC_EQ_RETRY;
                /* video info change */
                if ((!is_tmds_valid()) ||
                        (!rx_is_timing_stable())) {
@@ -2133,6 +2159,7 @@ void rx_main_state_machine(void)
                                rx.skip = 0;
                                rx.aud_sr_stable_cnt = 0;
                                rx.aud_sr_unstable_cnt = 0;
+                               esd_phy_rst_cnt = 0;
                                if (hdcp22_on) {
                                        esm_set_stable(false);
                                        if (esm_recovery_mode