CROSS_COMPILE = ppc_8xx-
endif
ifeq ($(ARCH),arm)
-CROSS_COMPILE = arm-linux-
+CROSS_COMPILE = /usr/local/arm/arm-2007q3/bin/arm-none-linux-gnueabi-
endif
ifeq ($(ARCH),i386)
CROSS_COMPILE = i386-linux-
omap3_zoom1_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 omap3 omap3
+s5pc100_tt_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 tt samsung s5pc100
+
#########################################################################
## XScale Systems
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := tt.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+
+# On SMDK6400 we use the 64 MB SDRAM bank at
+#
+# 0x50000000 to 0x58000000
+#
+# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
+#
+# we load ourselves to 0x57e00000 without MMU
+# with MMU, load address is changed to 0xc7e00000
+#
+# download area is 0x5000c000
+
+TEXT_BASE = 0x27e00000
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+#include <tt.h>
+
+#ifdef CONFIG_SERIAL1
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
+#elif defined(CONFIG_SERIAL2)
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
+#else
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
+#endif
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov r12, lr
+
+ /* LED on only #8 */
+ ldr r0, =ELFIN_GPIO_BASE
+ ldr r1, =0x55540000
+ str r1, [r0, #GPNCON_OFFSET]
+
+ ldr r1, =0x55555555
+ str r1, [r0, #GPNPUD_OFFSET]
+
+ ldr r1, =0xf000
+ str r1, [r0, #GPNDAT_OFFSET]
+
+ /* Disable Watchdog */
+ ldr r0, =0x7e000000 @0x7e004000
+ orr r0, r0, #0x4000
+ mov r1, #0
+ str r1, [r0]
+
+ /* External interrupt pending clear */
+ ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/
+ ldr r1, [r0]
+ str r1, [r0]
+
+ ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
+ ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
+
+ /* Disable all interrupts (VIC0 and VIC1) */
+ mvn r3, #0x0
+ str r3, [r0, #oINTMSK]
+ str r3, [r1, #oINTMSK]
+
+ /* Set all interrupts as IRQ */
+ mov r3, #0x0
+ str r3, [r0, #oINTMOD]
+ str r3, [r1, #oINTMOD]
+
+ /* Pending Interrupt Clear */
+ mov r3, #0x0
+ str r3, [r0, #oVECTADDR]
+ str r3, [r1, #oVECTADDR]
+
+ /* init system clock */
+ bl system_clock_init
+
+#ifndef CONFIG_NAND_SPL
+ /* for UART */
+ bl uart_asm_init
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+ /* simple init for NAND */
+ bl nand_asm_init
+#endif
+
+ /* Memory subsystem address 0x7e00f120 */
+ ldr r0, =ELFIN_MEM_SYS_CFG
+
+ /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
+ mov r1, #S3C64XX_MEM_SYS_CFG_NAND
+ str r1, [r0]
+
+ bl mem_ctrl_asm_init
+
+/* Wakeup support. Don't know if it's going to be used, untested. */
+ ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
+ ldr r1, [r0]
+ bic r1, r1, #0xfffffff7
+ cmp r1, #0x8
+ beq wakeup_reset
+
+1:
+ mov lr, r12
+ mov pc, lr
+
+wakeup_reset:
+
+ /* Clear wakeup status register */
+ ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
+ ldr r1, [r0]
+ str r1, [r0]
+
+ /* LED test */
+ ldr r0, =ELFIN_GPIO_BASE
+ ldr r1, =0x3000
+ str r1, [r0, #GPNDAT_OFFSET]
+
+ /* Load return address and jump to kernel */
+ ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
+ /* r1 = physical address of s3c6400_cpu_resume function */
+ ldr r1, [r0]
+ /* Jump to kernel (sleep-s3c6400.S) */
+ mov pc, r1
+ nop
+ nop
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+ ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */
+
+#ifdef CONFIG_SYNC_MODE
+ ldr r1, [r0, #OTHERS_OFFSET]
+ mov r2, #0x40
+ orr r1, r1, r2
+ str r1, [r0, #OTHERS_OFFSET]
+
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ ldr r2, =0x80
+ orr r1, r1, r2
+ str r1, [r0, #OTHERS_OFFSET]
+
+check_syncack:
+ ldr r1, [r0, #OTHERS_OFFSET]
+ ldr r2, =0xf00
+ and r1, r1, r2
+ cmp r1, #0xf00
+ bne check_syncack
+#else /* ASYNC Mode */
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /*
+ * This was unconditional in original Samsung sources, but it doesn't
+ * seem to make much sense on S3C6400.
+ */
+#ifndef CONFIG_S3C6400
+ ldr r1, [r0, #OTHERS_OFFSET]
+ bic r1, r1, #0xC0
+ orr r1, r1, #0x40
+ str r1, [r0, #OTHERS_OFFSET]
+
+wait_for_async:
+ ldr r1, [r0, #OTHERS_OFFSET]
+ and r1, r1, #0xf00
+ cmp r1, #0x0
+ bne wait_for_async
+#endif
+
+ ldr r1, [r0, #OTHERS_OFFSET]
+ bic r1, r1, #0x40
+ str r1, [r0, #OTHERS_OFFSET]
+#endif
+
+ mov r1, #0xff00
+ orr r1, r1, #0xff
+ str r1, [r0, #APLL_LOCK_OFFSET]
+ str r1, [r0, #MPLL_LOCK_OFFSET]
+
+ /* Set Clock Divider */
+ ldr r1, [r0, #CLK_DIV0_OFFSET]
+ bic r1, r1, #0x30000
+ bic r1, r1, #0xff00
+ bic r1, r1, #0xff
+ ldr r2, =CLK_DIV_VAL
+ orr r1, r1, r2
+ str r1, [r0, #CLK_DIV0_OFFSET]
+
+ ldr r1, =APLL_VAL
+ str r1, [r0, #APLL_CON_OFFSET]
+ ldr r1, =MPLL_VAL
+ str r1, [r0, #MPLL_CON_OFFSET]
+
+ /* FOUT of EPLL is 96MHz */
+ ldr r1, =0x200203
+ str r1, [r0, #EPLL_CON0_OFFSET]
+ ldr r1, =0x0
+ str r1, [r0, #EPLL_CON1_OFFSET]
+
+ /* APLL, MPLL, EPLL select to Fout */
+ ldr r1, [r0, #CLK_SRC_OFFSET]
+ orr r1, r1, #0x7
+ str r1, [r0, #CLK_SRC_OFFSET]
+
+ /* wait at least 200us to stablize all clock */
+ mov r1, #0x10000
+1: subs r1, r1, #1
+ bne 1b
+
+ /* Synchronization for VIC port */
+#if defined(CONFIG_SYNC_MODE)
+ ldr r1, [r0, #OTHERS_OFFSET]
+ orr r1, r1, #0x20
+ str r1, [r0, #OTHERS_OFFSET]
+#elif !defined(CONFIG_S3C6400)
+ /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
+ ldr r1, [r0, #OTHERS_OFFSET]
+ bic r1, r1, #0x20
+ str r1, [r0, #OTHERS_OFFSET]
+#endif
+ mov pc, lr
+
+
+#ifndef CONFIG_NAND_SPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+ /* set GPIO to enable UART */
+ ldr r0, =ELFIN_GPIO_BASE
+ ldr r1, =0x220022
+ str r1, [r0, #GPACON_OFFSET]
+ mov pc, lr
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+/*
+ * NAND Interface init for SMDK6400
+ */
+nand_asm_init:
+ ldr r0, =ELFIN_NAND_BASE
+ ldr r1, [r0, #NFCONF_OFFSET]
+ orr r1, r1, #0x70
+ orr r1, r1, #0x7700
+ str r1, [r0, #NFCONF_OFFSET]
+
+ ldr r1, [r0, #NFCONT_OFFSET]
+ orr r1, r1, #0x07
+ str r1, [r0, #NFCONT_OFFSET]
+
+ mov pc, lr
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+/*
+ * MMU Table for SMDK6400
+ */
+
+ /* form a first-level section entry */
+.macro FL_SECTION_ENTRY base,ap,d,c,b
+ .word (\base << 20) | (\ap << 10) | \
+ (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
+.endm
+
+.section .mmudata, "a"
+ .align 14
+ /* the following alignment creates the mmu table at address 0x4000. */
+ .globl mmu_table
+mmu_table:
+ .set __base, 0
+ /* 1:1 mapping for debugging */
+ .rept 0xA00
+ FL_SECTION_ENTRY __base, 3, 0, 0, 0
+ .set __base, __base + 1
+ .endr
+
+ /* access is not allowed. */
+ .rept 0xC00 - 0xA00
+ .word 0x00000000
+ .endr
+
+ /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
+ .set __base, 0x500
+ .rept 0xC80 - 0xC00
+ FL_SECTION_ENTRY __base, 3, 0, 1, 1
+ .set __base, __base + 1
+ .endr
+
+ /* access is not allowed. */
+ .rept 0x1000 - 0xc80
+ .word 0x00000000
+ .endr
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <tt.h>
+#include <flash.h>
+
+/* ------------------------------------------------------------------------- */
+#define CS8900_Tacs 0x0 /* 0clk address set-up */
+#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */
+#define CS8900_Tacc 0xE /* 14clk access cycle */
+#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */
+#define CS8900_Tah 0x4 /* 4clk address holding time */
+#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */
+#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */
+
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b"
+ : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+static void cs8900_pre_init(void)
+{
+ SROM_BW_REG &= ~(0xf << 4);
+ SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4);
+ SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) +
+ (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) +
+ (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC);
+}
+
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ cs8900_pre_init();
+
+ /* NOR-flash in SROM0 */
+
+ /* Enable WAIT */
+ SROM_BW_REG |= 4 | 8 | 1;
+
+ //gd->bd->bi_arch_number = MACH_TYPE;
+ gd->bd->bi_arch_number = 200;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+/*
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+*/
+
+#ifdef CONFIG_ENABLE_MMU
+ulong virt_to_phy_smdk6400(ulong addr)
+{
+ if ((0xc0000000 <= addr) && (addr < 0xc8000000))
+ return addr - 0xc0000000 + 0x50000000;
+ else
+ printf("do not support this address : %08lx\n", addr);
+
+ return addr;
+}
+#endif
+
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_SYS_NAND_LEGACY)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
+void nand_init(void)
+{
+ nand_probe(CONFIG_SYS_NAND_BASE);
+ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN)
+ print_size(nand_dev_desc[0].totlen, "\n");
+}
+#endif
+
+#if 1
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+ } else
+ return 0;
+}
+#endif
+
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm_cortexa8/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
+ __exidx_start = .;
+ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+ __exidx_end = .;
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+#!/bin/sh -x
+
+# Set default cross compiler
+CROSS_COMPILER=/usr/local/arm/arm-2007q3/bin/arm-none-linux-gnueabi-
+
+# Check this system has ccache
+check_ccache()
+{
+ type ccache
+ if [ "$?" -eq "0" ]; then
+ CCACHE=ccache
+ fi
+}
+
+build_uboot()
+{
+ make ARCH=arm CROSS_COMPILE="$CCACHE $CROSS_COMPILER" $JOBS $* -j 4
+}
+
+check_ccache
+
+build_uboot $*
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+SOBJS := lowlevel_init.o
+COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ *
+ * Common board functions for OMAP3 based boards.
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+
+/* inki */
+//extern omap3_sysinfo sysinfo;
+
+extern u32 is_mem_sdr(void);
+
+/******************************************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ *****************************************************************************/
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/******************************************************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ * (GP Device only)
+ *****************************************************************************/
+void secure_unlock_mem(void)
+{
+ pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
+ pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
+ pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
+ pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
+ sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;
+
+ /* Protection Module Register Target APE (PM_RT) */
+ writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
+ writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
+ writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
+ writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
+
+ writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
+ writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
+ writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
+
+ writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
+ writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
+ writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
+ writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
+
+ /* IVA Changes */
+ writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
+ writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
+ writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
+
+ /* SDRC region 0 public */
+ writel(UNLOCK_1, &sms_base->rg_att0);
+}
+
+/******************************************************************************
+ * Routine: secureworld_exit()
+ * Description: If chip is EMU and boot type is external
+ * configure secure registers and exit secure world
+ * general use.
+ *****************************************************************************/
+void secureworld_exit()
+{
+ unsigned long i;
+
+ /* configrue non-secure access control register */
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
+ /* enabling co-processor CP10 and CP11 accesses in NS world */
+ __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
+ /*
+ * allow allocation of locked TLBs and L2 lines in NS world
+ * allow use of PLE registers in NS world also
+ */
+ __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
+
+ /* Enable ASA in ACR register */
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+ __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+
+ /* Exiting secure world */
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
+ __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
+}
+
+/******************************************************************************
+ * Routine: setup_auxcr()
+ * Description: Write to AuxCR desired value using SMI.
+ * general use.
+ *****************************************************************************/
+void setup_auxcr()
+{
+ unsigned long i;
+ volatile unsigned int j;
+ /* Save r0, r12 and restore them after usage */
+ __asm__ __volatile__("mov %0, r12":"=r"(j));
+ __asm__ __volatile__("mov %0, r0":"=r"(i));
+
+ /*
+ * GP Device ROM code API usage here
+ * r12 = AUXCR Write function and r0 value
+ */
+ __asm__ __volatile__("mov r12, #0x3");
+ __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+ /* Enabling ASA */
+ __asm__ __volatile__("orr r0, r0, #0x10");
+ /* Enable L1NEON */
+ __asm__ __volatile__("orr r0, r0, #1 << 5");
+ /* SMI instruction to call ROM Code API */
+ __asm__ __volatile__(".word 0xE1600070");
+ __asm__ __volatile__("mov r0, %0":"=r"(i));
+ __asm__ __volatile__("mov r12, %0":"=r"(j));
+}
+
+/******************************************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP/EMU(special) type, unlock the SRAM for
+ * general use.
+ *****************************************************************************/
+void try_unlock_memory()
+{
+ int mode;
+ int in_sdram = is_running_in_sdram();
+
+ /*
+ * if GP device unlock device SRAM for general use
+ * secure code breaks for Secure/Emulation device - HS/E/T
+ */
+ mode = get_device_type();
+ if (mode == GP_DEVICE)
+ secure_unlock_mem();
+
+ /*
+ * If device is EMU and boot is XIP external booting
+ * Unlock firewalls and disable L2 and put chip
+ * out of secure world
+ *
+ * Assuming memories are unlocked by the demon who put us in SDRAM
+ */
+ if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
+ && (!in_sdram)) {
+ secure_unlock_mem();
+ secureworld_exit();
+ }
+
+ return;
+}
+
+/******************************************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with SRAM stack.
+ *****************************************************************************/
+void s_init(void)
+{
+ int in_sdram = is_running_in_sdram();
+
+ watchdog_init();
+
+ try_unlock_memory();
+
+ /*
+ * Right now flushing at low MPU speed.
+ * Need to move after clock init
+ */
+ v7_flush_dcache_all(get_device_type());
+#ifndef CONFIG_ICACHE_OFF
+ icache_enable();
+#endif
+
+#ifdef CONFIG_L2_OFF
+ l2cache_disable();
+#else
+ l2cache_enable();
+#endif
+ /*
+ * Writing to AuxCR in U-boot using SMI for GP DEV
+ * Currently SMI in Kernel on ES2 devices seems to have an issue
+ * Once that is resolved, we can postpone this config to kernel
+ */
+ if (get_device_type() == GP_DEVICE)
+ setup_auxcr();
+
+ /* inki */
+ //set_muxconf_regs();
+ delay(100);
+
+ prcm_init();
+
+ per_clocks_enable();
+
+ if (!in_sdram)
+ sdrc_init();
+}
+
+/******************************************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ *****************************************************************************/
+void wait_for_command_complete(watchdog_t *wd_base)
+{
+ int pending = 1;
+ do {
+ pending = readl(&wd_base->wwps);
+ } while (pending);
+}
+
+/******************************************************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************************************************/
+void watchdog_init(void)
+{
+ watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
+ prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+
+ /*
+ * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+ * either taken care of by ROM (HS/EMU) or not accessible (GP).
+ * We need to take care of WD2-MPU or take a PRCM reset. WD3
+ * should not be running and does not generate a PRCM reset.
+ */
+
+ sr32(&prcm_base->fclken_wkup, 5, 1, 1);
+ sr32(&prcm_base->iclken_wkup, 5, 1, 1);
+ wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
+
+ writel(WD_UNLOCK1, &wd2_base->wspr);
+ wait_for_command_complete(wd2_base);
+ writel(WD_UNLOCK2, &wd2_base->wspr);
+}
+
+/******************************************************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ *****************************************************************************/
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned int size0 = 0, size1 = 0;
+
+ /*
+ * If a second bank of DDR is attached to CS1 this is
+ * where it can be started. Early init code will init
+ * memory on CS0.
+ */
+ /* inki
+ if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+ do_sdrc_init(CS1, NOT_EARLY);
+ make_cs1_contiguous();
+ }
+ */
+
+ size0 = get_sdr_cs_size(CS0);
+ size1 = get_sdr_cs_size(CS1);
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = size0;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+ gd->bd->bi_dram[1].size = size1;
+
+ return 0;
+}
+
+/******************************************************************************
+ * Dummy function to handle errors for EABI incompatibility
+ *****************************************************************************/
+void raise(void)
+{
+}
+
+/******************************************************************************
+ * Dummy function to handle errors for EABI incompatibility
+ *****************************************************************************/
+void abort(void)
+{
+}
+
+#ifdef CONFIG_NAND_OMAP_GPMC
+/******************************************************************************
+ * OMAP3 specific command to switch between NAND HW and SW ecc
+ *****************************************************************************/
+static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc != 2)
+ goto usage;
+ if (strncmp(argv[1], "hw", 2) == 0)
+ omap_nand_switch_ecc(1);
+ else if (strncmp(argv[1], "sw", 2) == 0)
+ omap_nand_switch_ecc(0);
+ else
+ goto usage;
+
+ return 0;
+
+usage:
+ printf ("Usage: nandecc %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandecc, 2, 1, do_switch_ecc,
+ "nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
+ "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm\n"
+ );
+
+#endif /* CONFIG_NAND_OMAP_GPMC */
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+/**
+ * Print board information
+ */
+int checkboard (void)
+{
+ char *mem_s ;
+
+ if (is_mem_sdr())
+ mem_s = "mSDR";
+ else
+ mem_s = "LPDDR";
+
+ /* inki
+ printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
+ sysinfo.nand_string);
+ */
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and OMAP3 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/clocks_omap3.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <environment.h>
+#include <command.h>
+
+/******************************************************************************
+ * get_sys_clk_speed() - determine reference oscillator speed
+ * based on known 32kHz clock and gptimer.
+ *****************************************************************************/
+u32 get_osc_clk_speed(void)
+{
+ u32 start, cstart, cend, cdiff, val;
+ prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+ prm_t *prm_base = (prm_t *)PRM_BASE;
+ gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1;
+ s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE;
+
+ val = readl(&prm_base->clksrc_ctrl);
+
+ /* If SYS_CLK is being divided by 2, remove for now */
+ val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1;
+ writel(val, &prm_base->clksrc_ctrl);
+
+ /* enable timer2 */
+ val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
+
+ /* select sys_clk for GPT1 */
+ writel(val, &prcm_base->clksel_wkup);
+
+ /* Enable I and F Clocks for GPT1 */
+ val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
+ writel(val, &prcm_base->iclken_wkup);
+ val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
+ writel(val, &prcm_base->fclken_wkup);
+
+ writel(0, &gpt1_base->tldr); /* start counting at 0 */
+ writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
+
+ /* enable 32kHz source, determine sys_clk via gauging */
+
+ /* start time in 20 cycles */
+ start = 20 + readl(&s32k_base->s32k_cr);
+
+ /* dead loop till start time */
+ while (readl(&s32k_base->s32k_cr) < start);
+
+ /* get start sys_clk count */
+ cstart = readl(&gpt1_base->tcrr);
+
+ /* wait for 40 cycles */
+ while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
+ cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
+ cdiff = cend - cstart; /* get elapsed ticks */
+
+ /* based on number of ticks assign speed */
+ if (cdiff > 19000)
+ return S38_4M;
+ else if (cdiff > 15200)
+ return S26M;
+ else if (cdiff > 13000)
+ return S24M;
+ else if (cdiff > 9000)
+ return S19_2M;
+ else if (cdiff > 7600)
+ return S13M;
+ else
+ return S12M;
+}
+
+/******************************************************************************
+ * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
+ * input oscillator clock frequency.
+ *****************************************************************************/
+void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
+{
+ switch(osc_clk) {
+ case S38_4M:
+ *sys_clkin_sel = 4;
+ break;
+ case S26M:
+ *sys_clkin_sel = 3;
+ break;
+ case S19_2M:
+ *sys_clkin_sel = 2;
+ break;
+ case S13M:
+ *sys_clkin_sel = 1;
+ break;
+ case S12M:
+ default:
+ *sys_clkin_sel = 0;
+ }
+}
+
+/******************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ * called from SRAM, or Flash (using temp SRAM stack).
+ *****************************************************************************/
+void prcm_init(void)
+{
+ void (*f_lock_pll) (u32, u32, u32, u32);
+ int xip_safe, p0, p1, p2, p3;
+ u32 osc_clk = 0, sys_clkin_sel;
+ u32 clk_index, sil_index = 0;
+ prm_t *prm_base = (prm_t *)PRM_BASE;
+ prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+ dpll_param *dpll_param_p;
+
+ f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
+ SRAM_VECT_CODE);
+
+ xip_safe = is_running_in_sram();
+
+ /*
+ * Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ osc_clk = get_osc_clk_speed();
+ get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+
+ /* set input crystal speed */
+ sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
+
+ /* If the input clock is greater than 19.2M always divide/2 */
+ if (sys_clkin_sel > 2) {
+ /* input clock divider */
+ sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
+ clk_index = sys_clkin_sel / 2;
+ } else {
+ /* input clock divider */
+ sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
+ clk_index = sys_clkin_sel;
+ }
+
+ /*
+ * The DPLL tables are defined according to sysclk value and
+ * silicon revision. The clk_index value will be used to get
+ * the values for that input sysclk from the DPLL param table
+ * and sil_index will get the values for that SysClk for the
+ * appropriate silicon rev.
+ */
+ if (get_cpu_rev())
+ sil_index = 1;
+
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);
+
+ /* Getting the base address of Core DPLL param table */
+ dpll_param_p = (dpll_param *) get_core_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+ if (xip_safe) {
+ /*
+ * CORE DPLL
+ * sr32(CM_CLKSEL2_EMU) set override to work when asleep
+ */
+ sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
+ LDELAY);
+
+ /*
+ * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
+ * work. write another value and then default value.
+ */
+
+ /* m3x2 */
+ sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2 + 1);
+ /* m3x2 */
+ sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
+ /* Set M2 */
+ sr32(&prcm_base->clksel1_pll, 27, 2, dpll_param_p->m2);
+ /* Set M */
+ sr32(&prcm_base->clksel1_pll, 16, 11, dpll_param_p->m);
+ /* Set N */
+ sr32(&prcm_base->clksel1_pll, 8, 7, dpll_param_p->n);
+ /* 96M Src */
+ sr32(&prcm_base->clksel1_pll, 6, 1, 0);
+ /* ssi */
+ sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
+ /* fsusb */
+ sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
+ /* l4 */
+ sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
+ /* l3 */
+ sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
+ /* gfx */
+ sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
+ /* reset mgr */
+ sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
+ /* FREQSEL */
+ sr32(&prcm_base->clken_pll, 4, 4, dpll_param_p->fsel);
+ /* lock mode */
+ sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
+
+ wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
+ LDELAY);
+ } else if (is_running_in_flash()) {
+ /*
+ * if running from flash, jump to small relocated code
+ * area in SRAM.
+ */
+ p0 = readl(&prcm_base->clken_pll);
+ sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ sr32(&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+
+ p1 = readl(&prcm_base->clksel1_pll);
+ sr32(&p1, 27, 2, dpll_param_p->m2); /* Set M2 */
+ sr32(&p1, 16, 11, dpll_param_p->m); /* Set M */
+ sr32(&p1, 8, 7, dpll_param_p->n); /* Set N */
+ sr32(&p1, 6, 1, 0); /* set source for 96M */
+
+ p2 = readl(&prcm_base->clksel_core);
+ sr32(&p2, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(&p2, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32(&p2, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(&p2, 0, 2, CORE_L3_DIV); /* l3 */
+
+ p3 = (u32)&prcm_base->idlest_ckgen;
+
+ (*f_lock_pll) (p0, p1, p2, p3);
+ }
+
+ /* PER DPLL */
+ sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
+ wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
+
+ /* Getting the base address to PER DPLL param table */
+
+ /* Set N */
+ dpll_param_p = (dpll_param *) get_per_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ dpll_param_p = dpll_param_p + clk_index;
+
+ /*
+ * Errata 1.50 Workaround for OMAP3 ES1.0 only
+ * If using default divisors, write default divisor + 1
+ * and then the actual divisor value
+ */
+ sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2 + 1); /* set M6 */
+ sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); /* set M6 */
+ sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2 + 1); /* set M5 */
+ sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); /* set M5 */
+ sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2 + 1); /* set M4 */
+ sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); /* set M4 */
+ sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2 + 1); /* set M3 */
+ sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); /* set M3 */
+ sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2 + 1); /* set M2 */
+ sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2); /* set M2 */
+ /* Workaround end */
+
+ sr32(&prcm_base->clksel2_pll, 8, 11, dpll_param_p->m); /* set m */
+ sr32(&prcm_base->clksel2_pll, 0, 7, dpll_param_p->n); /* set n */
+ sr32(&prcm_base->clken_pll, 20, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
+
+ /* Getting the base address to MPU DPLL param table */
+ dpll_param_p = (dpll_param *) get_mpu_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+
+ /* MPU DPLL (unlocked already) */
+
+ /* Set M2 */
+ sr32(&prcm_base->clksel2_pll_mpu, 0, 5, dpll_param_p->m2);
+ /* Set M */
+ sr32(&prcm_base->clksel1_pll_mpu, 8, 11, dpll_param_p->m);
+ /* Set N */
+ sr32(&prcm_base->clksel1_pll_mpu, 0, 7, dpll_param_p->n);
+ /* FREQSEL */
+ sr32(&prcm_base->clken_pll_mpu, 4, 4, dpll_param_p->fsel);
+ /* lock mode */
+ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
+ wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);
+
+ /* Getting the base address to IVA DPLL param table */
+ dpll_param_p = (dpll_param *) get_iva_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+
+ /* IVA DPLL (set to 12*20=240MHz) */
+ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
+ wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
+ /* set M2 */
+ sr32(&prcm_base->clksel2_pll_iva2, 0, 5, dpll_param_p->m2);
+ /* set M */
+ sr32(&prcm_base->clksel1_pll_iva2, 8, 11, dpll_param_p->m);
+ /* set N */
+ sr32(&prcm_base->clksel1_pll_iva2, 0, 7, dpll_param_p->n);
+ /* FREQSEL */
+ sr32(&prcm_base->clken_pll_iva2, 4, 4, dpll_param_p->fsel);
+ /* lock mode */
+ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
+ wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
+
+ /* Set up GPTimers to sys_clk source only */
+ sr32(&prcm_base->clksel_per, 0, 8, 0xff);
+ sr32(&prcm_base->clksel_wkup, 0, 1, 1);
+
+ sdelay(5000);
+}
+
+/******************************************************************************
+ * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
+ *****************************************************************************/
+void per_clocks_enable(void)
+{
+ prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+
+ /* Enable GP2 timer. */
+ sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
+ sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
+ sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
+
+#ifdef CONFIG_SYS_NS16550
+ /* Enable UART1 clocks */
+ sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
+ sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
+
+ /* UART 3 Clocks */
+ sr32(&prcm_base->fclken_per, 11, 1, 0x1);
+ sr32(&prcm_base->iclken_per, 11, 1, 0x1);
+#endif
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ /* Turn on all 3 I2C clocks */
+ sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
+ sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
+#endif
+ /* Enable the ICLK for 32K Sync Timer as its used in udelay */
+ sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
+
+ sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
+ sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
+ sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
+ sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
+ sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
+ sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
+ sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
+ sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
+ sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
+ sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+ sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
+ sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
+
+ sdelay(1000);
+}
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v7a.
+PLATFORM_CPPFLAGS += -march=armv5
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+ $(call cc-option,-malignment-traps,))
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Moahmmed Khasim <khasim@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/proc-armv/ptrace.h>
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts(void)
+{
+ unsigned long temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "bic %0, %0, #0x80\n" "msr cpsr_c, %0":"=r"(temp)
+ ::"memory");
+}
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts(void)
+{
+ unsigned long old, temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "orr %1, %0, #0xc0\n"
+ "msr cpsr_c, %1":"=r"(old), "=r"(temp)
+ ::"memory");
+ return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts(void)
+{
+ return;
+}
+int disable_interrupts(void)
+{
+ return 0;
+}
+#endif
+
+void bad_mode(void)
+{
+ panic("Resetting CPU ...\n");
+ reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+ unsigned long flags;
+ const char *processor_modes[] = {
+ "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
+ "UK4_26", "UK5_26", "UK6_26", "UK7_26",
+ "UK8_26", "UK9_26", "UK10_26", "UK11_26",
+ "UK12_26", "UK13_26", "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
+ "UK4_32", "UK5_32", "UK6_32", "ABT_32",
+ "UK8_32", "UK9_32", "UK10_32", "UND_32",
+ "UK12_32", "UK13_32", "UK14_32", "SYS_32",
+ };
+
+ flags = condition_codes(regs);
+
+ printf("pc : [<%08lx>] lr : [<%08lx>]\n"
+ "sp : %08lx ip : %08lx fp : %08lx\n",
+ instruction_pointer(regs),
+ regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+ printf("r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+ printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+ printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+ printf("Flags: %c%c%c%c",
+ flags & CC_N_BIT ? 'N' : 'n',
+ flags & CC_Z_BIT ? 'Z' : 'z',
+ flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+ printf(" IRQs %s FIQs %s Mode %s%s\n",
+ interrupts_enabled(regs) ? "on" : "off",
+ fast_interrupts_enabled(regs) ? "on" : "off",
+ processor_modes[processor_mode(regs)],
+ thumb_mode(regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction(struct pt_regs *pt_regs)
+{
+ printf("undefined instruction\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_software_interrupt(struct pt_regs *pt_regs)
+{
+ printf("software interrupt\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_prefetch_abort(struct pt_regs *pt_regs)
+{
+ printf("prefetch abort\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_data_abort(struct pt_regs *pt_regs)
+{
+ printf("data abort\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_not_used(struct pt_regs *pt_regs)
+{
+ printf("not used\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_fiq(struct pt_regs *pt_regs)
+{
+ printf("fast interrupt request\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_irq(struct pt_regs *pt_regs)
+{
+ printf("interrupt request\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+
+static ulong timestamp;
+static ulong lastinc;
+static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Nothing really to do with interrupts, just starts up a counter.
+ * We run the counter with 13MHz, divided by 8, resulting in timer
+ * frequency of 1.625MHz. With 32bit counter register, counter
+ * overflows in ~44min
+ */
+
+/* 13MHz / 8 = 1.625MHz */
+#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
+#define TIMER_LOAD_VAL 0xffffffff
+
+int interrupt_init(void)
+{
+ /* start the counter ticking up, reload value on overflow */
+ writel(TIMER_LOAD_VAL, &timer_base->tldr);
+ /* enable timer */
+ writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
+ &timer_base->tclr);
+
+ reset_timer_masked(); /* init the timestamp and lastinc value */
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds */
+void udelay(unsigned long usec)
+{
+ long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+ unsigned long now, last = readl(&timer_base->tcrr);
+
+ while (tmo > 0) {
+ now = readl(&timer_base->tcrr);
+ if (last > now) /* count up timer overflow */
+ tmo -= TIMER_LOAD_VAL - last + now;
+ else
+ tmo -= now - last;
+ last = now;
+ }
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time, capture current incrementer value time */
+ lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked(void)
+{
+ /* current tick value */
+ ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+
+ if (now >= lastinc) /* normal mode (non roll) */
+ /* move stamp fordward with absoulte diff ticks */
+ timestamp += (now - lastinc);
+ else /* we have rollover of incrementer */
+ timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
+ - lastinc) + now;
+ lastinc = now;
+ return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
--- /dev/null
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Initial Code by:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks_omap3.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3 - r10} /* copy from source address [r0] */
+ stmia r1!, {r3 - r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/* ***************************************************************************
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = CM_CLKEN_PLL-bypass value
+ * R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ * R2 = CM_CLKSEL_CORE-divider values
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ * Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ * confused. A reset of the controller gets it back. Taking away its
+ * L3 when its not in self refresh seems bad for it. Normally, this
+ * code runs from flash before SDR is init so that should be ok.
+ ****************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ stmfd sp!, {r4 - r6}
+
+ /* move into fast relock bypass */
+ ldr r4, pll_ctl_add
+ str r0, [r4]
+wait1:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ beq wait1 /* if lock, loop */
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r5, pll_div_add1
+ str r1, [r5] /* set m, n, m2 */
+ ldr r5, pll_div_add2
+ str r2, [r5] /* set l3/l4/.. dividers*/
+ ldr r5, pll_div_add3 /* wkup */
+ ldr r2, pll_div_val3 /* rsm val */
+ str r2, [r5]
+ ldr r5, pll_div_add4 /* gfx */
+ ldr r2, pll_div_val4
+ str r2, [r5]
+ ldr r5, pll_div_add5 /* emu */
+ ldr r2, pll_div_val5
+ str r2, [r5]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r5, flash_cfg3_addr
+ ldr r2, flash_cfg3_val
+ str r2, [r5]
+ ldr r5, flash_cfg4_addr
+ ldr r2, flash_cfg4_val
+ str r2, [r5]
+ ldr r5, flash_cfg5_addr
+ ldr r2, flash_cfg5_val
+ str r2, [r5]
+ ldr r5, flash_cfg1_addr
+ ldr r2, [r5]
+ orr r2, r2, #0x3 /* up gpmc divider */
+ str r2, [r5]
+
+ /* lock DPLL3 and wait a bit */
+ orr r0, r0, #0x7 /* set up for lock mode */
+ str r0, [r4] /* lock */
+ nop /* ARM slow at this point working at sys_clk */
+ nop
+ nop
+ nop
+wait2:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ bne wait2 /* if lock, loop */
+ nop
+ nop
+ nop
+ nop
+ ldmfd sp!, {r4 - r6}
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val:
+ .word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+ .word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+ .word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_div_add1:
+ .word CM_CLKSEL1_PLL
+pll_div_add2:
+ .word CM_CLKSEL_CORE
+pll_div_add3:
+ .word CM_CLKSEL_WKUP
+pll_div_val3:
+ .word (WKUP_RSM << 1)
+pll_div_add4:
+ .word CM_CLKSEL_GFX
+pll_div_val4:
+ .word (GFX_DIV << 0)
+pll_div_add5:
+ .word CM_CLKSEL1_EMU
+pll_div_val5:
+ .word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll, mux, memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
+/* DPLL(1-4) PARAM TABLES */
+
+/*
+ * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
+/* ES2 */
+.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
+/* 3410 */
+.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
+
+/* 13MHz */
+/* ES1 */
+.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
+/* ES2 */
+.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
+/* 3410 */
+.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
+/* ES2 */
+.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
+/* 3410 */
+.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
+
+/* 26MHz */
+/* ES1 */
+.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
+/* ES2 */
+.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
+/* 3410 */
+.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
+/* ES2 */
+.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
+/* 3410 */
+.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+ adr r0, mpu_dpll_param
+ mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
+/* ES2 */
+.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
+/* 3410 */
+.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
+
+/* 13MHz */
+/* ES1 */
+.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
+/* ES2 */
+.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
+/* 3410 */
+.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
+/* ES2 */
+.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
+/* 3410 */
+.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
+
+/* 26MHz */
+/* ES1 */
+.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
+/* ES2 */
+.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
+/* 3410 */
+.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
+/* ES2 */
+.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
+/* 3410 */
+.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+ adr r0, iva_dpll_param
+ mov pc, lr
+
+/* Core DPLL targets for L3 at 166 & L133 */
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
+/* ES2 */
+.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
+/* 3410 */
+.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
+
+/* 13MHz */
+/* ES1 */
+.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
+/* ES2 */
+.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
+/* 3410 */
+.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
+/* ES2 */
+.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
+/* 3410 */
+.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
+
+/* 26MHz */
+/* ES1 */
+.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
+/* ES2 */
+.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
+/* 3410 */
+.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
+/* ES2 */
+.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
+/* 3410 */
+.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+ adr r0, core_dpll_param
+ mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
+
+/* 13MHz */
+.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
+
+/* 19.2MHz */
+.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
+
+/* 26MHz */
+.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
+
+/* 38.4MHz */
+.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+ adr r0, per_dpll_param
+ mov pc, lr
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Initial Code from:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <command.h>
+
+/*
+ * Only One NAND allowed on board at a time.
+ * The GPMC CS Base for the same
+ */
+unsigned int boot_flash_base;
+unsigned int boot_flash_off;
+unsigned int boot_flash_sec;
+unsigned int boot_flash_type;
+volatile unsigned int boot_flash_env_addr;
+
+#if defined(CONFIG_CMD_NAND)
+static u32 gpmc_m_nand[GPMC_MAX_REG] = {
+ M_NAND_GPMC_CONFIG1,
+ M_NAND_GPMC_CONFIG2,
+ M_NAND_GPMC_CONFIG3,
+ M_NAND_GPMC_CONFIG4,
+ M_NAND_GPMC_CONFIG5,
+ M_NAND_GPMC_CONFIG6, 0
+};
+
+gpmc_csx_t *nand_cs_base;
+gpmc_t *gpmc_cfg_base;
+
+#if defined(CONFIG_ENV_IS_IN_NAND)
+#define GPMC_CS 0
+#else
+#define GPMC_CS 1
+#endif
+
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+static u32 gpmc_onenand[GPMC_MAX_REG] = {
+ ONENAND_GPMC_CONFIG1,
+ ONENAND_GPMC_CONFIG2,
+ ONENAND_GPMC_CONFIG3,
+ ONENAND_GPMC_CONFIG4,
+ ONENAND_GPMC_CONFIG5,
+ ONENAND_GPMC_CONFIG6, 0
+};
+
+gpmc_csx_t *onenand_cs_base;
+
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+#define GPMC_CS 0
+#else
+#define GPMC_CS 1
+#endif
+
+#endif
+
+static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
+
+/**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ * command line mem=xyz use all memory with out discontinuous support
+ * compiled in. Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **************************************************************************/
+void make_cs1_contiguous(void)
+{
+ u32 size, a_add_low, a_add_high;
+
+ size = get_sdr_cs_size(CS0);
+ size /= SZ_32M; /* find size to offset CS1 */
+ a_add_high = (size & 3) << 8; /* set up low field */
+ a_add_low = (size & 0x3C) >> 2; /* set up high field */
+ writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
+
+}
+
+/********************************************************
+ * mem_ok() - test used to see if timings are correct
+ * for a part. Helps in guessing which part
+ * we are currently using.
+ *******************************************************/
+u32 mem_ok(u32 cs)
+{
+ u32 val1, val2, addr;
+ u32 pattern = 0x12345678;
+
+ addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
+
+ writel(0x0, addr + 0x400); /* clear pos A */
+ writel(pattern, addr); /* pattern to pos B */
+ writel(0x0, addr + 4); /* remove pattern off the bus */
+ val1 = readl(addr + 0x400); /* get pos A value */
+ val2 = readl(addr); /* get val2 */
+
+ if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
+ return 0;
+ else
+ return 1;
+}
+
+/********************************************************
+ * sdrc_init() - init the sdrc chip selects CS0 and CS1
+ * - early init routines, called from flash or
+ * SRAM.
+ *******************************************************/
+void sdrc_init(void)
+{
+ /* only init up first bank here */
+ do_sdrc_init(CS0, EARLY_INIT);
+}
+
+/*************************************************************************
+ * do_sdrc_init(): initialize the SDRAM for use.
+ * -code sets up SDRAM basic SDRC timings for CS0
+ * -optimal settings can be placed here, or redone after i2c
+ * inspection of board info
+ *
+ * - code called once in C-Stack only context for CS0 and a possible 2nd
+ * time depending on memory configuration from stack+global context
+ **************************************************************************/
+
+void do_sdrc_init(u32 cs, u32 early)
+{
+ sdrc_actim_t *sdrc_actim_base;
+
+ if(cs)
+ sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL1_BASE;
+ else
+ sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL0_BASE;
+
+ if (early) {
+ /* reset sdrc controller */
+ writel(SOFTRESET, &sdrc_base->sysconfig);
+ wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
+ 12000000);
+ writel(0, &sdrc_base->sysconfig);
+
+ /* setup sdrc to ball mux */
+ writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
+
+ /* Disable Power Down of CKE cuz of 1 CKE on combo part */
+ writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
+
+ writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
+ sdelay(0x20000);
+ }
+
+ writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
+ RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
+ DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
+ writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
+ writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
+ writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
+
+ writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
+ writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+
+ /*
+ * CAS latency 3, Write Burst = Read Burst, Serial Mode,
+ * Burst length = 4
+ */
+ writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
+
+ if (!mem_ok(cs))
+ writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
+void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base, u32 base,
+ u32 size)
+{
+ writel(0, &gpmc_cs_base->config7);
+ sdelay(1000);
+ /* Delay for settling */
+ writel(gpmc_config[0], &gpmc_cs_base->config1);
+ writel(gpmc_config[1], &gpmc_cs_base->config2);
+ writel(gpmc_config[2], &gpmc_cs_base->config3);
+ writel(gpmc_config[3], &gpmc_cs_base->config4);
+ writel(gpmc_config[4], &gpmc_cs_base->config5);
+ writel(gpmc_config[5], &gpmc_cs_base->config6);
+ /* Enable the config */
+ writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+ (1 << 6)), &gpmc_cs_base->config7);
+ sdelay(2000);
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+ /* putting a blanket check on GPMC based on ZeBu for now */
+ u32 *gpmc_config = NULL;
+ gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
+ gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
+ u32 base = 0;
+ u32 size = 0;
+ u32 f_off = CONFIG_SYS_MONITOR_LEN;
+ u32 f_sec = 0;
+ u32 config = 0;
+
+ /* global settings */
+ writel(0, &gpmc_base->irqenable); /* isr's sources masked */
+ writel(0, &gpmc_base->timeout_control);/* timeout disable */
+
+ config = readl(&gpmc_base->config);
+ config &= (~0xf00);
+ writel(config, &gpmc_base->config);
+
+ /*
+ * Disable the GPMC0 config set by ROM code
+ * It conflicts with our MPDB (both at 0x08000000)
+ */
+ writel(0, &gpmc_cs_base->config7);
+ sdelay(1000);
+
+#if defined(CONFIG_CMD_NAND) /* CS 0 */
+ gpmc_config = gpmc_m_nand;
+ gpmc_cfg_base = gpmc_base;
+ nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
+ (GPMC_CS * GPMC_CONFIG_WIDTH));
+ base = PISMO1_NAND_BASE;
+ size = PISMO1_NAND_SIZE;
+ enable_gpmc_config(gpmc_config, nand_cs_base, base, size);
+#if defined(CONFIG_ENV_IS_IN_NAND)
+ f_off = SMNAND_ENV_OFFSET;
+ f_sec = SZ_128K;
+ /* env setup */
+ boot_flash_base = base;
+ boot_flash_off = f_off;
+ boot_flash_sec = f_sec;
+ boot_flash_env_addr = f_off;
+#endif
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+ gpmc_config = gpmc_onenand;
+ onenand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
+ (GPMC_CS * GPMC_CONFIG_WIDTH));
+ base = PISMO1_ONEN_BASE;
+ size = PISMO1_ONEN_SIZE;
+ enable_gpmc_config(gpmc_config, onenand_cs_base, base, size);
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+ f_off = ONENAND_ENV_OFFSET;
+ f_sec = SZ_128K;
+ /* env setup */
+ boot_flash_base = base;
+ boot_flash_off = f_off;
+ boot_flash_sec = f_sec;
+ boot_flash_env_addr = f_off;
+#endif
+#endif
+}
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h> /* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+
+extern omap3_sysinfo sysinfo;
+static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
+static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
+static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+static char *rev_s[CPU_3XX_MAX_REV] = {
+ "1.0",
+ "2.0",
+ "2.1",
+ "3.0",
+ "3.1"};
+
+/*****************************************************************
+ * dieid_num_r(void) - read and set die ID
+ *****************************************************************/
+void dieid_num_r(void)
+{
+ ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE;
+ char *uid_s, die_id[34];
+ u32 id[4];
+
+ memset(die_id, 0, sizeof(die_id));
+
+ uid_s = getenv("dieid#");
+
+ if (uid_s == NULL) {
+ id[3] = readl(&id_base->die_id_0);
+ id[2] = readl(&id_base->die_id_1);
+ id[1] = readl(&id_base->die_id_2);
+ id[0] = readl(&id_base->die_id_3);
+ sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
+ setenv("dieid#", die_id);
+ uid_s = die_id;
+ }
+
+ printf("Die ID #%s\n", uid_s);
+}
+
+/******************************************
+ * get_cpu_type(void) - extract cpu info
+ ******************************************/
+u32 get_cpu_type(void)
+{
+ return readl(&ctrl_base->ctrl_omap_stat);
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 cpuid = 0;
+ ctrl_id_t *id_base;
+
+ /*
+ * On ES1.0 the IDCODE register is not exposed on L4
+ * so using CPU ID to differentiate between ES1.0 and > ES1.0.
+ */
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
+ if ((cpuid & 0xf) == 0x0)
+ return CPU_3XX_ES10;
+ else {
+ /* Decode the IDs on > ES1.0 */
+ id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
+
+ cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
+
+ /* Some early ES2.0 seem to report ID 0, fix this */
+ if(cpuid == 0)
+ cpuid = CPU_3XX_ES20;
+
+ return cpuid;
+ }
+}
+
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+ if (readl(&sdrc_base->cs[CS0].mr) == SDP_SDRC_MR_0_SDR)
+ return 1;
+ return 0;
+}
+
+/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 cs)
+{
+ u32 size;
+
+ /* get ram size field */
+ size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
+ size &= 0x3FF; /* remove unwanted bits */
+ size *= SZ_2M; /* find size in MB */
+ return size;
+}
+
+/***********************************************************************
+ * get_sdr_cs_offset() - get offset of cs from cs0 start
+ ************************************************************************/
+u32 get_sdr_cs_offset(u32 cs)
+{
+ u32 offset;
+
+ if (!cs)
+ return 0;
+
+ offset = readl(&sdrc_base->cs_cfg);
+ offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+
+ return offset;
+}
+
+/***************************************************************************
+ * get_gpmc0_base() - Return current address hardware will be
+ * fetching from. The below effectively gives what is correct, its a bit
+ * mis-leading compared to the TRM. For the most general case the mask
+ * needs to be also taken into account this does work in practice.
+ * - for u-boot we currently map:
+ * -- 0 to nothing,
+ * -- 4 to flash
+ * -- 8 to enent
+ * -- c to wifi
+ ****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+ u32 b;
+
+ b = readl(&gpmc_cs_base->config7);
+ b &= 0x1F; /* keep base [5:0] */
+ b = b << 24; /* ret 0x0b000000 */
+ return b;
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+ return WIDTH_16BIT;
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ *************************************************************************/
+u32 get_board_rev(void)
+{
+ return 0x20;
+}
+
+/********************************************************
+ * get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+ u32 val;
+
+ __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+ val &= 0xF0000000;
+ val >>= 28;
+ return val;
+}
+
+/********************************************************
+ * is_running_in_flash() - tell if currently running in
+ * FLASH.
+ *******************************************************/
+u32 is_running_in_flash(void)
+{
+ if (get_base() < 4)
+ return 1; /* in FLASH */
+
+ return 0; /* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ * is_running_in_sram() - tell if currently running in
+ * SRAM.
+ *******************************************************/
+u32 is_running_in_sram(void)
+{
+ if (get_base() == 4)
+ return 1; /* in SRAM */
+
+ return 0; /* running in FLASH or SDRAM */
+}
+
+/********************************************************
+ * is_running_in_sdram() - tell if currently running in
+ * SDRAM.
+ *******************************************************/
+u32 is_running_in_sdram(void)
+{
+ if (get_base() > 4)
+ return 1; /* in SDRAM */
+
+ return 0; /* running in SRAM or FLASH */
+}
+
+/***************************************************************
+ * get_boot_type() - Is this an XIP type device or a stream one
+ * bits 4-0 specify type. Bit 5 says mem/perif
+ ***************************************************************/
+u32 get_boot_type(void)
+{
+ return (readl(&ctrl_base->status) & SYSBOOT_MASK);
+}
+
+/*************************************************************
+ * get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+ return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/**
+ * Print CPU information
+ */
+int print_cpuinfo (void)
+{
+ char *cpu_s, *sec_s;
+
+ switch (get_cpu_type()) {
+ case OMAP3503:
+ cpu_s = "3503";
+ break;
+ case OMAP3515:
+ cpu_s = "3515";
+ break;
+ case OMAP3525:
+ cpu_s = "3525";
+ break;
+ case OMAP3530:
+ cpu_s = "3530";
+ break;
+ default:
+ cpu_s = "35XX";
+ break;
+ }
+
+ switch (get_device_type()) {
+ case TST_DEVICE:
+ sec_s = "TST";
+ break;
+ case EMU_DEVICE:
+ sec_s = "EMU";
+ break;
+ case HS_DEVICE:
+ sec_s = "HS";
+ break;
+ case GP_DEVICE:
+ sec_s = "GP";
+ break;
+ default:
+ sec_s = "?";
+ }
+
+ printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n",
+ cpu_s, sec_s, rev_s[get_cpu_rev()]);
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+
+/************************************************************
+ * sdelay() - simple spin loop. Will be constant time as
+ * its generally used in bypass conditions only. This
+ * is necessary until timers are accessible.
+ *
+ * not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*****************************************************************
+ * sr32 - clear & set a value in a bit range for a 32 bit address
+ *****************************************************************/
+void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+ msk = 1 << num_bits;
+ --msk;
+ tmp = readl((u32)addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ writel(tmp, (u32)addr);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ * volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+ u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = readl((u32)read_addr) & read_bit_mask;
+ if (val == match_value)
+ return 1;
+ if (i == bound)
+ return 0;
+ } while (1);
+}
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_H_
+#define _CLOCKS_H_
+
+#define LDELAY 12000000
+
+#define S12M 12000000
+#define S13M 13000000
+#define S19_2M 19200000
+#define S24M 24000000
+#define S26M 26000000
+#define S38_4M 38400000
+
+#define FCK_IVA2_ON 0x00000001
+#define FCK_CORE1_ON 0x03fffe29
+#define ICK_CORE1_ON 0x3ffffffb
+#define ICK_CORE2_ON 0x0000001f
+#define FCK_WKUP_ON 0x000000e9
+#define ICK_WKUP_ON 0x0000003f
+#define FCK_DSS_ON 0x00000005
+#define ICK_DSS_ON 0x00000001
+#define FCK_CAM_ON 0x00000001
+#define ICK_CAM_ON 0x00000001
+#define FCK_PER_ON 0x0003ffff
+#define ICK_PER_ON 0x0003ffff
+
+/* Used to index into DPLL parameter tables */
+typedef struct {
+ unsigned int m;
+ unsigned int n;
+ unsigned int fsel;
+ unsigned int m2;
+} dpll_param;
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param *get_mpu_dpll_param(void);
+extern dpll_param *get_iva_dpll_param(void);
+extern dpll_param *get_core_dpll_param(void);
+extern dpll_param *get_per_dpll_param(void);
+
+extern void *_end_vect, *_start;
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP3_H_
+#define _CLOCKS_OMAP3_H_
+
+#define PLL_STOP 1 /* PER & IVA */
+#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
+#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
+#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
+
+/*
+ * The following configurations are OPP and SysClk value independant
+ * and hence are defined here. All the other DPLL related values are
+ * tabulated in lowlevel_init.S.
+ */
+
+/* CORE DPLL */
+#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
+#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
+#define CORE_FUSB_DIV 2 /* 41.5MHz: */
+#define CORE_L4_DIV 2 /* 83MHz : L4 */
+#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
+#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
+#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
+
+/* PER DPLL */
+#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
+#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
+#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */
+#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
+
+#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
+
+/* MPU DPLL */
+
+#define MPU_M_12_ES1 0x0FE
+#define MPU_N_12_ES1 0x07
+#define MPU_FSEL_12_ES1 0x05
+#define MPU_M2_12_ES1 0x01
+
+#define MPU_M_12_ES2 0x0FA
+#define MPU_N_12_ES2 0x05
+#define MPU_FSEL_12_ES2 0x07
+#define MPU_M2_ES2 0x01
+
+#define MPU_M_12 0x085
+#define MPU_N_12 0x05
+#define MPU_FSEL_12 0x07
+#define MPU_M2_12 0x01
+
+#define MPU_M_13_ES1 0x17D
+#define MPU_N_13_ES1 0x0C
+#define MPU_FSEL_13_ES1 0x03
+#define MPU_M2_13_ES1 0x01
+
+#define MPU_M_13_ES2 0x1F4
+#define MPU_N_13_ES2 0x0C
+#define MPU_FSEL_13_ES2 0x03
+#define MPU_M2_13_ES2 0x01
+
+#define MPU_M_13 0x10A
+#define MPU_N_13 0x0C
+#define MPU_FSEL_13 0x03
+#define MPU_M2_13 0x01
+
+#define MPU_M_19P2_ES1 0x179
+#define MPU_N_19P2_ES1 0x12
+#define MPU_FSEL_19P2_ES1 0x04
+#define MPU_M2_19P2_ES1 0x01
+
+#define MPU_M_19P2_ES2 0x271
+#define MPU_N_19P2_ES2 0x17
+#define MPU_FSEL_19P2_ES2 0x03
+#define MPU_M2_19P2_ES2 0x01
+
+#define MPU_M_19P2 0x14C
+#define MPU_N_19P2 0x17
+#define MPU_FSEL_19P2 0x03
+#define MPU_M2_19P2 0x01
+
+#define MPU_M_26_ES1 0x17D
+#define MPU_N_26_ES1 0x19
+#define MPU_FSEL_26_ES1 0x03
+#define MPU_M2_26_ES1 0x01
+
+#define MPU_M_26_ES2 0x0FA
+#define MPU_N_26_ES2 0x0C
+#define MPU_FSEL_26_ES2 0x07
+#define MPU_M2_26_ES2 0x01
+
+#define MPU_M_26 0x085
+#define MPU_N_26 0x0C
+#define MPU_FSEL_26 0x07
+#define MPU_M2_26 0x01
+
+#define MPU_M_38P4_ES1 0x1FA
+#define MPU_N_38P4_ES1 0x32
+#define MPU_FSEL_38P4_ES1 0x03
+#define MPU_M2_38P4_ES1 0x01
+
+#define MPU_M_38P4_ES2 0x271
+#define MPU_N_38P4_ES2 0x2F
+#define MPU_FSEL_38P4_ES2 0x03
+#define MPU_M2_38P4_ES2 0x01
+
+#define MPU_M_38P4 0x14C
+#define MPU_N_38P4 0x2F
+#define MPU_FSEL_38P4 0x03
+#define MPU_M2_38P4 0x01
+
+/* IVA DPLL */
+
+#define IVA_M_12_ES1 0x07D
+#define IVA_N_12_ES1 0x05
+#define IVA_FSEL_12_ES1 0x07
+#define IVA_M2_12_ES1 0x01
+
+#define IVA_M_12_ES2 0x0B4
+#define IVA_N_12_ES2 0x05
+#define IVA_FSEL_12_ES2 0x07
+#define IVA_M2_12_ES2 0x01
+
+#define IVA_M_12 0x085
+#define IVA_N_12 0x05
+#define IVA_FSEL_12 0x07
+#define IVA_M2_12 0x01
+
+#define IVA_M_13_ES1 0x0FA
+#define IVA_N_13_ES1 0x0C
+#define IVA_FSEL_13_ES1 0x03
+#define IVA_M2_13_ES1 0x01
+
+#define IVA_M_13_ES2 0x168
+#define IVA_N_13_ES2 0x0C
+#define IVA_FSEL_13_ES2 0x03
+#define IVA_M2_13_ES2 0x01
+
+#define IVA_M_13 0x10A
+#define IVA_N_13 0x0C
+#define IVA_FSEL_13 0x03
+#define IVA_M2_13 0x01
+
+#define IVA_M_19P2_ES1 0x082
+#define IVA_N_19P2_ES1 0x09
+#define IVA_FSEL_19P2_ES1 0x07
+#define IVA_M2_19P2_ES1 0x01
+
+#define IVA_M_19P2_ES2 0x0E1
+#define IVA_N_19P2_ES2 0x0B
+#define IVA_FSEL_19P2_ES2 0x06
+#define IVA_M2_19P2_ES2 0x01
+
+#define IVA_M_19P2 0x14C
+#define IVA_N_19P2 0x17
+#define IVA_FSEL_19P2 0x03
+#define IVA_M2_19P2 0x01
+
+#define IVA_M_26_ES1 0x07D
+#define IVA_N_26_ES1 0x0C
+#define IVA_FSEL_26_ES1 0x07
+#define IVA_M2_26_ES1 0x01
+
+#define IVA_M_26_ES2 0x0B4
+#define IVA_N_26_ES2 0x0C
+#define IVA_FSEL_26_ES2 0x07
+#define IVA_M2_26_ES2 0x01
+
+#define IVA_M_26 0x085
+#define IVA_N_26 0x0C
+#define IVA_FSEL_26 0x07
+#define IVA_M2_26 0x01
+
+#define IVA_M_38P4_ES1 0x13F
+#define IVA_N_38P4_ES1 0x30
+#define IVA_FSEL_38P4_ES1 0x03
+#define IVA_M2_38P4_ES1 0x01
+
+#define IVA_M_38P4_ES2 0x0E1
+#define IVA_N_38P4_ES2 0x17
+#define IVA_FSEL_38P4_ES2 0x06
+#define IVA_M2_38P4_ES2 0x01
+
+#define IVA_M_38P4 0x14C
+#define IVA_N_38P4 0x2F
+#define IVA_FSEL_38P4 0x03
+#define IVA_M2_38P4 0x01
+
+/* CORE DPLL */
+
+#define CORE_M_12 0xA6
+#define CORE_N_12 0x05
+#define CORE_FSEL_12 0x07
+#define CORE_M2_12 0x01 /* M3 of 2 */
+
+#define CORE_M_12_ES1 0x19F
+#define CORE_N_12_ES1 0x0E
+#define CORE_FSL_12_ES1 0x03
+#define CORE_M2_12_ES1 0x1 /* M3 of 2 */
+
+#define CORE_M_13 0x14C
+#define CORE_N_13 0x0C
+#define CORE_FSEL_13 0x03
+#define CORE_M2_13 0x01 /* M3 of 2 */
+
+#define CORE_M_13_ES1 0x1B2
+#define CORE_N_13_ES1 0x10
+#define CORE_FSL_13_ES1 0x03
+#define CORE_M2_13_ES1 0x01 /* M3 of 2 */
+
+#define CORE_M_19P2 0x19F
+#define CORE_N_19P2 0x17
+#define CORE_FSEL_19P2 0x03
+#define CORE_M2_19P2 0x01 /* M3 of 2 */
+
+#define CORE_M_19P2_ES1 0x19F
+#define CORE_N_19P2_ES1 0x17
+#define CORE_FSL_19P2_ES1 0x03
+#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */
+
+#define CORE_M_26 0xA6
+#define CORE_N_26 0x0C
+#define CORE_FSEL_26 0x07
+#define CORE_M2_26 0x01 /* M3 of 2 */
+
+#define CORE_M_26_ES1 0x1B2
+#define CORE_N_26_ES1 0x21
+#define CORE_FSL_26_ES1 0x03
+#define CORE_M2_26_ES1 0x01 /* M3 of 2 */
+
+#define CORE_M_38P4 0x19F
+#define CORE_N_38P4 0x2F
+#define CORE_FSEL_38P4 0x03
+#define CORE_M2_38P4 0x01 /* M3 of 2 */
+
+#define CORE_M_38P4_ES1 0x19F
+#define CORE_N_38P4_ES1 0x2F
+#define CORE_FSL_38P4_ES1 0x03
+#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */
+
+/* PER DPLL */
+
+#define PER_M_12 0xD8
+#define PER_N_12 0x05
+#define PER_FSEL_12 0x07
+#define PER_M2_12 0x09
+
+#define PER_M_13 0x1B0
+#define PER_N_13 0x0C
+#define PER_FSEL_13 0x03
+#define PER_M2_13 0x09
+
+#define PER_M_19P2 0xE1
+#define PER_N_19P2 0x09
+#define PER_FSEL_19P2 0x07
+#define PER_M2_19P2 0x09
+
+#define PER_M_26 0xD8
+#define PER_N_26 0x0C
+#define PER_FSEL_26 0x07
+#define PER_M2_26 0x09
+
+#define PER_M_38P4 0xE1
+#define PER_N_38P4 0x13
+#define PER_FSEL_38P4 0x07
+#define PER_M2_38P4 0x09
+
+#endif /* endif _CLOCKS_OMAP3_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+/* Register offsets of common modules */
+/* Control */
+#ifndef __ASSEMBLY__
+typedef struct ctrl {
+ unsigned char res1[0xC0];
+ unsigned short gpmc_nadv_ale; /* 0xC0 */
+ unsigned short gpmc_noe; /* 0xC2 */
+ unsigned short gpmc_nwe; /* 0xC4 */
+ unsigned char res2[0x22A];
+ unsigned int status; /* 0x2F0 */
+ unsigned int gpstatus; /* 0x2F4 */
+ unsigned char res3[0x08];
+ unsigned int rpubkey_0; /* 0x300 */
+ unsigned int rpubkey_1; /* 0x304 */
+ unsigned int rpubkey_2; /* 0x308 */
+ unsigned int rpubkey_3; /* 0x30C */
+ unsigned int rpubkey_4; /* 0x310 */
+ unsigned char res4[0x04];
+ unsigned int randkey_0; /* 0x318 */
+ unsigned int randkey_1; /* 0x31C */
+ unsigned int randkey_2; /* 0x320 */
+ unsigned int randkey_3; /* 0x324 */
+ unsigned char res5[0x124];
+ unsigned int ctrl_omap_stat; /* 0x44C */
+} ctrl_t;
+#else /* __ASSEMBLY__ */
+#define CONTROL_STATUS 0x2F0
+#endif /* __ASSEMBLY__ */
+
+/* cpu type */
+#define OMAP3503 0x5c00
+#define OMAP3515 0x1c00
+#define OMAP3525 0x4c00
+#define OMAP3530 0x0c00
+
+#ifndef __ASSEMBLY__
+typedef struct ctrl_id {
+ unsigned char res1[0x4];
+ unsigned int idcode; /* 0x04 */
+ unsigned int prod_id; /* 0x08 */
+ unsigned char res2[0x0C];
+ unsigned int die_id_0; /* 0x18 */
+ unsigned int die_id_1; /* 0x1C */
+ unsigned int die_id_2; /* 0x20 */
+ unsigned int die_id_3; /* 0x24 */
+} ctrl_id_t;
+#endif /* __ASSEMBLY__ */
+
+/* device type */
+#define DEVICE_MASK (0x7 << 8)
+#define SYSBOOT_MASK 0x1F
+#define TST_DEVICE 0x0
+#define EMU_DEVICE 0x1
+#define HS_DEVICE 0x2
+#define GP_DEVICE 0x3
+
+/* GPMC CS3/cs4/cs6 not avaliable */
+#define GPMC_BASE (OMAP34XX_GPMC_BASE)
+#define GPMC_CONFIG_CS0 0x60
+#define GPMC_CONFIG_CS6 0x150
+#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
+#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
+#define GPMC_CONFIG_WP 0x10
+
+#define GPMC_CONFIG_WIDTH 0x30
+
+#ifndef __ASSEMBLY__
+typedef struct gpmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned char res2[0x4];
+ unsigned int irqstatus; /* 0x18 */
+ unsigned int irqenable; /* 0x1C */
+ unsigned char res3[0x20];
+ unsigned int timeout_control; /* 0x40 */
+ unsigned char res4[0xC];
+ unsigned int config; /* 0x50 */
+ unsigned int status; /* 0x54 */
+ unsigned char res5[0x19C];
+ unsigned int ecc_config; /* 0x1F4 */
+ unsigned int ecc_control; /* 0x1F8 */
+ unsigned int ecc_size_config; /* 0x1FC */
+ unsigned int ecc1_result; /* 0x200 */
+ unsigned int ecc2_result; /* 0x204 */
+ unsigned int ecc3_result; /* 0x208 */
+ unsigned int ecc4_result; /* 0x20C */
+ unsigned int ecc5_result; /* 0x210 */
+ unsigned int ecc6_result; /* 0x214 */
+ unsigned int ecc7_result; /* 0x218 */
+ unsigned int ecc8_result; /* 0x21C */
+ unsigned int ecc9_result; /* 0x220 */
+} gpmc_t;
+
+typedef struct gpmc_csx {
+ unsigned int config1; /* 0x00 */
+ unsigned int config2; /* 0x04 */
+ unsigned int config3; /* 0x08 */
+ unsigned int config4; /* 0x0C */
+ unsigned int config5; /* 0x10 */
+ unsigned int config6; /* 0x14 */
+ unsigned int config7; /* 0x18 */
+ unsigned int nand_cmd; /* 0x1C */
+ unsigned int nand_adr; /* 0x20 */
+ unsigned int nand_dat; /* 0x24 */
+} gpmc_csx_t;
+#else /* __ASSEMBLY__ */
+#define GPMC_CONFIG1 0x00
+#define GPMC_CONFIG2 0x04
+#define GPMC_CONFIG3 0x08
+#define GPMC_CONFIG4 0x0C
+#define GPMC_CONFIG5 0x10
+#define GPMC_CONFIG6 0x14
+#define GPMC_CONFIG7 0x18
+#endif /* __ASSEMBLY__ */
+
+/* GPMC Mapping */
+#define FLASH_BASE 0x10000000 /* NOR flash, */
+ /* aligned to 256 Meg */
+#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
+ /* aligned to 64 Meg */
+#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
+ /* aligned to 256 Meg */
+#define DEBUG_BASE 0x08000000 /* debug board */
+#define NAND_BASE 0x30000000 /* NAND addr */
+ /* (actual size small port) */
+#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
+#define ONENAND_MAP 0x20000000 /* OneNand addr */
+ /* (actual size small port) */
+/* SMS */
+#ifndef __ASSEMBLY__
+typedef struct sms {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned char res2[0x34];
+ unsigned int rg_att0; /* 0x48 */
+ unsigned char res3[0x84];
+ unsigned int class_arb0; /* 0xD0 */
+} sms_t;
+#endif /* __ASSEMBLY__ */
+
+#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
+
+/* SDRC */
+#ifndef __ASSEMBLY__
+typedef struct sdrc_cs {
+ unsigned int mcfg; /* 0x80 || 0xB0 */
+ unsigned int mr; /* 0x84 || 0xB4 */
+ unsigned char res1[0x4];
+ unsigned int emr2; /* 0x8C || 0xBC */
+ unsigned char res2[0x14];
+ unsigned int rfr_ctrl; /* 0x84 || 0xD4 */
+ unsigned int manual; /* 0xA8 || 0xD8 */
+ unsigned char res3[0x4];
+} sdrc_cs_t;
+
+typedef struct sdrc_actim {
+ unsigned int ctrla; /* 0x9C || 0xC4 */
+ unsigned int ctrlb; /* 0xA0 || 0xC8 */
+} sdrc_actim_t;
+
+typedef struct sdrc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int status; /* 0x14 */
+ unsigned char res2[0x28];
+ unsigned int cs_cfg; /* 0x40 */
+ unsigned int sharing; /* 0x44 */
+ unsigned char res3[0x18];
+ unsigned int dlla_ctrl; /* 0x60 */
+ unsigned int dlla_status; /* 0x64 */
+ unsigned int dllb_ctrl; /* 0x68 */
+ unsigned int dllb_status; /* 0x6C */
+ unsigned int power; /* 0x70 */
+ unsigned char res4[0xC];
+ sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */
+} sdrc_t;
+#endif /* __ASSEMBLY__ */
+
+#define DLLPHASE_90 (0x1 << 1)
+#define LOADDLL (0x1 << 2)
+#define ENADLL (0x1 << 3)
+#define DLL_DELAY_MASK 0xFF00
+#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
+
+#define PAGEPOLICY_HIGH (0x1 << 0)
+#define SRFRONRESET (0x1 << 7)
+#define WAKEUPPROC (0x1 << 26)
+
+#define DDR_SDRAM (0x1 << 0)
+#define DEEPPD (0x1 << 3)
+#define B32NOT16 (0x1 << 4)
+#define BANKALLOCATION (0x2 << 6)
+#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
+#define ADDRMUXLEGACY (0x1 << 19)
+#define CASWIDTH_10BITS (0x5 << 20)
+#define RASWIDTH_13BITS (0x2 << 24)
+#define BURSTLENGTH4 (0x2 << 0)
+#define CASL3 (0x3 << 4)
+#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
+#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
+#define ARE_ARCV_1 (0x1 << 0)
+#define ARCV (0x4e2 << 8) /* Autorefresh count */
+#define OMAP34XX_SDRC_CS0 0x80000000
+#define OMAP34XX_SDRC_CS1 0xA0000000
+#define CMD_NOP 0x0
+#define CMD_PRECHARGE 0x1
+#define CMD_AUTOREFRESH 0x2
+#define CMD_ENTR_PWRDOWN 0x3
+#define CMD_EXIT_PWRDOWN 0x4
+#define CMD_ENTR_SRFRSH 0x5
+#define CMD_CKE_HIGH 0x6
+#define CMD_CKE_LOW 0x7
+#define SOFTRESET (0x1 << 1)
+#define SMART_IDLE (0x2 << 3)
+#define REF_ON_IDLE (0x1 << 6)
+
+/* timer regs offsets (32 bit regs) */
+
+#ifndef __ASSEMBLY__
+typedef struct gptimer {
+ unsigned int tidr; /* 0x00 r */
+ unsigned char res[0xc];
+ unsigned int tiocp_cfg; /* 0x10 rw */
+ unsigned int tistat; /* 0x14 r */
+ unsigned int tisr; /* 0x18 rw */
+ unsigned int tier; /* 0x1c rw */
+ unsigned int twer; /* 0x20 rw */
+ unsigned int tclr; /* 0x24 rw */
+ unsigned int tcrr; /* 0x28 rw */
+ unsigned int tldr; /* 0x2c rw */
+ unsigned int ttgr; /* 0x30 rw */
+ unsigned int twpc; /* 0x34 r*/
+ unsigned int tmar; /* 0x38 rw*/
+ unsigned int tcar1; /* 0x3c r */
+ unsigned int tcicr; /* 0x40 rw */
+ unsigned int tcar2; /* 0x44 r */
+} gptimer_t;
+#endif /* __ASSEMBLY__ */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __ASSEMBLY__
+typedef struct watchdog {
+ unsigned char res1[0x34];
+ unsigned int wwps; /* 0x34 r */
+ unsigned char res2[0x10];
+ unsigned int wspr; /* 0x48 rw */
+} watchdog_t;
+#endif /* __ASSEMBLY__ */
+
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+/* PRCM */
+#define PRCM_BASE 0x48004000
+
+#ifndef __ASSEMBLY__
+typedef struct prcm {
+ unsigned int fclken_iva2; /* 0x00 */
+ unsigned int clken_pll_iva2; /* 0x04 */
+ unsigned char res1[0x1c];
+ unsigned int idlest_pll_iva2; /* 0x24 */
+ unsigned char res2[0x18];
+ unsigned int clksel1_pll_iva2 ; /* 0x40 */
+ unsigned int clksel2_pll_iva2; /* 0x44 */
+ unsigned char res3[0x8bc];
+ unsigned int clken_pll_mpu; /* 0x904 */
+ unsigned char res4[0x1c];
+ unsigned int idlest_pll_mpu; /* 0x924 */
+ unsigned char res5[0x18];
+ unsigned int clksel1_pll_mpu; /* 0x940 */
+ unsigned int clksel2_pll_mpu; /* 0x944 */
+ unsigned char res6[0xb8];
+ unsigned int fclken1_core; /* 0xa00 */
+ unsigned char res7[0xc];
+ unsigned int iclken1_core; /* 0xa10 */
+ unsigned int iclken2_core; /* 0xa14 */
+ unsigned char res8[0x28];
+ unsigned int clksel_core; /* 0xa40 */
+ unsigned char res9[0xbc];
+ unsigned int fclken_gfx; /* 0xb00 */
+ unsigned char res10[0xc];
+ unsigned int iclken_gfx; /* 0xb10 */
+ unsigned char res11[0x2c];
+ unsigned int clksel_gfx; /* 0xb40 */
+ unsigned char res12[0xbc];
+ unsigned int fclken_wkup; /* 0xc00 */
+ unsigned char res13[0xc];
+ unsigned int iclken_wkup; /* 0xc10 */
+ unsigned char res14[0xc];
+ unsigned int idlest_wkup; /* 0xc20 */
+ unsigned char res15[0x1c];
+ unsigned int clksel_wkup; /* 0xc40 */
+ unsigned char res16[0xbc];
+ unsigned int clken_pll; /* 0xd00 */
+ unsigned char res17[0x1c];
+ unsigned int idlest_ckgen; /* 0xd20 */
+ unsigned char res18[0x1c];
+ unsigned int clksel1_pll; /* 0xd40 */
+ unsigned int clksel2_pll; /* 0xd44 */
+ unsigned int clksel3_pll; /* 0xd48 */
+ unsigned char res19[0xb4];
+ unsigned int fclken_dss; /* 0xe00 */
+ unsigned char res20[0xc];
+ unsigned int iclken_dss; /* 0xe10 */
+ unsigned char res21[0x2c];
+ unsigned int clksel_dss; /* 0xe40 */
+ unsigned char res22[0xbc];
+ unsigned int fclken_cam; /* 0xf00 */
+ unsigned char res23[0xc];
+ unsigned int iclken_cam; /* 0xf10 */
+ unsigned char res24[0x2c];
+ unsigned int clksel_cam; /* 0xf40 */
+ unsigned char res25[0xbc];
+ unsigned int fclken_per; /* 0x1000 */
+ unsigned char res26[0xc];
+ unsigned int iclken_per; /* 0x1010 */
+ unsigned char res27[0x2c];
+ unsigned int clksel_per; /* 0x1040 */
+ unsigned char res28[0xfc];
+ unsigned int clksel1_emu; /* 0x1140 */
+} prcm_t;
+#else /* __ASSEMBLY__ */
+#define CM_CLKSEL_CORE 0x48004a40
+#define CM_CLKSEL_GFX 0x48004b40
+#define CM_CLKSEL_WKUP 0x48004c40
+#define CM_CLKEN_PLL 0x48004d00
+#define CM_CLKSEL1_PLL 0x48004d40
+#define CM_CLKSEL1_EMU 0x48005140
+#endif /* __ASSEMBLY__ */
+
+#define PRM_BASE 0x48306000
+
+#ifndef __ASSEMBLY__
+typedef struct prm {
+ unsigned char res1[0xd40];
+ unsigned int clksel; /* 0xd40 */
+ unsigned char res2[0x50c];
+ unsigned int rstctrl; /* 0x1250 */
+ unsigned char res3[0x1c];
+ unsigned int clksrc_ctrl; /* 0x1270 */
+} prm_t;
+#else /* __ASSEMBLY__ */
+#define PRM_RSTCTRL 0x48307250
+#endif /* __ASSEMBLY__ */
+
+#define SYSCLKDIV_1 (0x1 << 6)
+#define SYSCLKDIV_2 (0x1 << 7)
+
+#define CLKSEL_GPT1 (0x1 << 0)
+
+#define EN_GPT1 (0x1 << 0)
+#define EN_32KSYNC (0x1 << 2)
+
+#define ST_WDT2 (0x1 << 5)
+
+#define ST_MPU_CLK (0x1 << 0)
+
+#define ST_CORE_CLK (0x1 << 0)
+
+#define ST_PERIPH_CLK (0x1 << 1)
+
+#define ST_IVA2_CLK (0x1 << 0)
+
+#define RESETDONE (0x1 << 0)
+
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/* SMX-APE */
+#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
+#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
+#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
+#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
+
+#ifndef __ASSEMBLY__
+typedef struct pm {
+ unsigned char res1[0x48];
+ unsigned int req_info_permission_0; /* 0x48 */
+ unsigned char res2[0x4];
+ unsigned int read_permission_0; /* 0x50 */
+ unsigned char res3[0x4];
+ unsigned int wirte_permission_0; /* 0x58 */
+ unsigned char res4[0x4];
+ unsigned int addr_match_1; /* 0x58 */
+ unsigned char res5[0x4];
+ unsigned int req_info_permission_1; /* 0x68 */
+ unsigned char res6[0x14];
+ unsigned int addr_match_2; /* 0x80 */
+} pm_t;
+#endif /*__ASSEMBLY__ */
+
+/* Permission values for registers -Full fledged permissions to all */
+#define UNLOCK_1 0xFFFFFFFF
+#define UNLOCK_2 0x00000000
+#define UNLOCK_3 0x0000FFFF
+
+#define NOT_EARLY 0
+
+/* I2C base */
+#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
+#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
+#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
+
+#endif /* _CPU_H */
--- /dev/null
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ARCH_HARDWARE_H_
+#define _ARCH_HARDWARE_H_
+
+#include <asm/sizes.h>
+
+#ifndef __ASSEMBLY__
+#define UData(Data) ((unsigned long) (Data))
+
+#define __REG(x) (*(vu_long *)(x))
+#define __REGl(x) (*(vu_long *)(x))
+#define __REGw(x) (*(vu_short *)(x))
+#define __REGb(x) (*(vu_char *)(x))
+#define __REG2(x, y) (*(vu_long *)((x) + (y)))
+#else
+#define UData(Data) (Data)
+
+#define __REG(x) (x)
+#define __REGl(x) (x)
+#define __REGw(x) (x)
+#define __REGb(x) (x)
+#define __REG2(x, y) ((x) + (y))
+#endif
+
+#define Fld(Size, Shft) (((Size) << 16) + (Shft))
+
+#define FSize(Field) ((Field) >> 16)
+#define FShft(Field) ((Field) & 0x0000FFFF)
+#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field) (UData (1) << FShft (Field))
+
+#define FClrBit(Data, Bit) (Data = (Data & ~(Bit)))
+#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field)))
+
+#define FInsrt(Value, Field) \
+ (UData (Value) << FShft (Field))
+
+#define FExtr(Data, Field) \
+ ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+#endif /* _ARCH_HARDWARE_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _I2C_H_
+#define _I2C_H_
+
+#define I2C_DEFAULT_BASE I2C_BASE1
+
+#define I2C_REV (I2C_DEFAULT_BASE + 0x00)
+#define I2C_IE (I2C_DEFAULT_BASE + 0x04)
+#define I2C_STAT (I2C_DEFAULT_BASE + 0x08)
+#define I2C_IV (I2C_DEFAULT_BASE + 0x0c)
+#define I2C_BUF (I2C_DEFAULT_BASE + 0x14)
+#define I2C_CNT (I2C_DEFAULT_BASE + 0x18)
+#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c)
+#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20)
+#define I2C_CON (I2C_DEFAULT_BASE + 0x24)
+#define I2C_OA (I2C_DEFAULT_BASE + 0x28)
+#define I2C_SA (I2C_DEFAULT_BASE + 0x2c)
+#define I2C_PSC (I2C_DEFAULT_BASE + 0x30)
+#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34)
+#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38)
+#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c)
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE (1 << 5)
+#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD (1 << 15) /* Single byte data */
+#define I2C_STAT_BB (1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS (1 << 9) /* Address as slave */
+#define I2C_STAT_GC (1 << 5)
+#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
+#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
+#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
+#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK 7
+#define I2C_INTCODE_NONE 0
+#define I2C_INTCODE_AL 1 /* Arbitration lost */
+#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY 3 /* Register access ready */
+#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
+#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
+#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN (1 << 15) /* I2C module enable */
+#define I2C_CON_BE (1 << 14) /* Big endian mode */
+#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
+#define I2C_CON_MST (1 << 10) /* Master/slave mode */
+#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
+ /* (master mode only) */
+#define I2C_CON_XA (1 << 8) /* Expand address */
+#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
+#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
+#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
+#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
+#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
+
+#define I2C_SCLL_SCLL 0
+#define I2C_SCLL_SCLL_M 0xFF
+#define I2C_SCLL_HSSCLL 8
+#define I2C_SCLH_HSSCLL_M 0xFF
+#define I2C_SCLH_SCLH 0
+#define I2C_SCLH_SCLH_M 0xFF
+#define I2C_SCLH_HSSCLH 8
+#define I2C_SCLH_HSSCLH_M 0xFF
+
+#define OMAP_I2C_STANDARD 100
+#define OMAP_I2C_FAST_MODE 400
+#define OMAP_I2C_HIGH_SPEED 3400
+
+#define SYSTEM_CLOCK_12 12000
+#define SYSTEM_CLOCK_13 13000
+#define SYSTEM_CLOCK_192 19200
+#define SYSTEM_CLOCK_96 96000
+
+#define I2C_IP_CLK SYSTEM_CLOCK_96
+#define I2C_PSC_MAX 0x0f
+#define I2C_PSC_MIN 0x00
+
+#endif /* _I2C_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+#define CS0 0x0
+#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
+
+#ifndef __ASSEMBLY__
+typedef enum {
+ STACKED = 0,
+ IP_DDR = 1,
+ COMBO_DDR = 2,
+ IP_SDR = 3,
+} mem_t;
+#endif /* __ASSEMBLY__ */
+
+#define EARLY_INIT 1
+
+/* Slower full frequency range default timings for x32 operation*/
+#define SDP_SDRC_SHARING 0x00000100
+#define SDP_SDRC_MR_0_SDR 0x00000031
+
+/* optimized timings good for current shipping parts */
+#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+
+#define DLL_OFFSET 0
+#define DLL_WRITEDDRCLKX2DIS 1
+#define DLL_ENADLL 1
+#define DLL_LOCKDLL 0
+#define DLL_DLLPHASE_72 0
+#define DLL_DLLPHASE_90 1
+
+/* rkw - need to find of 90/72 degree recommendation for speed like before */
+#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
+ (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
+
+/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
+ * ACTIMA
+ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
+ * TDPL (Twr) = 15/6 = 2.5 -> 3
+ * TRRD = 12/6 = 2
+ * TRCD = 18/6 = 3
+ * TRP = 18/6 = 3
+ * TRAS = 42/6 = 7
+ * TRC = 60/6 = 10
+ * TRFC = 72/6 = 12
+ * ACTIMB
+ * TCKE = 2
+ * XSR = 120/6 = 20
+ */
+#define TDAL_165 6
+#define TDPL_165 3
+#define TRRD_165 2
+#define TRCD_165 3
+#define TRP_165 3
+#define TRAS_165 7
+#define TRC_165 10
+#define TRFC_165 21
+#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
+ (TRAS_165 << 18) | (TRP_165 << 15) | \
+ (TRCD_165 << 12) | (TRRD_165 << 9) | \
+ (TDPL_165 << 6) | (TDAL_165))
+
+#define TWTR_165 1
+#define TCKE_165 1
+#define TXP_165 5
+#define XSR_165 23
+#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
+ (TXP_165 << 8) | (TWTR_165 << 16))
+
+#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
+#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
+#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * STNOR - Intel Strata Flash
+ * SMNAND - Samsung NAND
+ * MPDB - H4 MPDB board
+ * SBNOR - Sibley NOR
+ * MNAND - Micron Large page x16 NAND
+ * ONNAND - Samsung One NAND
+ *
+ * include/configs/file.h contains the defn - for all CS we are interested
+ * #define OMAP34XX_GPMC_CSx PART
+ * #define OMAP34XX_GPMC_CSx_SIZE Size
+ * #define OMAP34XX_GPMC_CSx_MAP Map
+ * Where:
+ * x - CS number
+ * PART - Part Name as defined above
+ * SIZE - how big is the mapping to be
+ * GPMC_SIZE_128M - 0x8
+ * GPMC_SIZE_64M - 0xC
+ * GPMC_SIZE_32M - 0xE
+ * GPMC_SIZE_16M - 0xF
+ * MAP - Map this CS to which address(GPMC address space)- Absolute address
+ * >>24 before being used.
+ */
+#define GPMC_SIZE_128M 0x8
+#define GPMC_SIZE_64M 0xC
+#define GPMC_SIZE_32M 0xE
+#define GPMC_SIZE_16M 0xF
+
+#define SMNAND_GPMC_CONFIG1 0x00000800
+#define SMNAND_GPMC_CONFIG2 0x00141400
+#define SMNAND_GPMC_CONFIG3 0x00141400
+#define SMNAND_GPMC_CONFIG4 0x0F010F01
+#define SMNAND_GPMC_CONFIG5 0x010C1414
+#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
+#define SMNAND_GPMC_CONFIG7 0x00000C44
+
+#define M_NAND_GPMC_CONFIG1 0x00001800
+#define M_NAND_GPMC_CONFIG2 0x00141400
+#define M_NAND_GPMC_CONFIG3 0x00141400
+#define M_NAND_GPMC_CONFIG4 0x0F010F01
+#define M_NAND_GPMC_CONFIG5 0x010C1414
+#define M_NAND_GPMC_CONFIG6 0x1f0f0A80
+#define M_NAND_GPMC_CONFIG7 0x00000C44
+
+#define STNOR_GPMC_CONFIG1 0x3
+#define STNOR_GPMC_CONFIG2 0x00151501
+#define STNOR_GPMC_CONFIG3 0x00060602
+#define STNOR_GPMC_CONFIG4 0x11091109
+#define STNOR_GPMC_CONFIG5 0x01141F1F
+#define STNOR_GPMC_CONFIG6 0x000004c4
+
+#define SIBNOR_GPMC_CONFIG1 0x1200
+#define SIBNOR_GPMC_CONFIG2 0x001f1f00
+#define SIBNOR_GPMC_CONFIG3 0x00080802
+#define SIBNOR_GPMC_CONFIG4 0x1C091C09
+#define SIBNOR_GPMC_CONFIG5 0x01131F1F
+#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
+
+#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
+#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
+#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
+#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
+#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
+#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
+
+#define MPDB_GPMC_CONFIG1 0x00011000
+#define MPDB_GPMC_CONFIG2 0x001f1f01
+#define MPDB_GPMC_CONFIG3 0x00080803
+#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
+#define MPDB_GPMC_CONFIG5 0x041f1F1F
+#define MPDB_GPMC_CONFIG6 0x1F0F04C4
+
+#define P2_GPMC_CONFIG1 0x0
+#define P2_GPMC_CONFIG2 0x0
+#define P2_GPMC_CONFIG3 0x0
+#define P2_GPMC_CONFIG4 0x0
+#define P2_GPMC_CONFIG5 0x0
+#define P2_GPMC_CONFIG6 0x0
+
+#define ONENAND_GPMC_CONFIG1 0x00001200
+#define ONENAND_GPMC_CONFIG2 0x000F0F01
+#define ONENAND_GPMC_CONFIG3 0x00030301
+#define ONENAND_GPMC_CONFIG4 0x0F040F04
+#define ONENAND_GPMC_CONFIG5 0x010F1010
+#define ONENAND_GPMC_CONFIG6 0x1F060000
+
+#define NET_GPMC_CONFIG1 0x00001000
+#define NET_GPMC_CONFIG2 0x001e1e01
+#define NET_GPMC_CONFIG3 0x00080300
+#define NET_GPMC_CONFIG4 0x1c091c09
+#define NET_GPMC_CONFIG5 0x04181f1f
+#define NET_GPMC_CONFIG6 0x00000FCF
+#define NET_GPMC_CONFIG7 0x00000f6c
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS 8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG 7
+
+#define PISMO1_NOR 1
+#define PISMO1_NAND 2
+#define PISMO2_CS0 3
+#define PISMO2_CS1 4
+#define PISMO1_ONENAND 5
+#define DBG_MPDB 6
+#define PISMO2_NAND_CS0 7
+#define PISMO2_NAND_CS1 8
+
+/* make it readable for the gpmc_init */
+#define PISMO1_NOR_BASE FLASH_BASE
+#define PISMO1_NAND_BASE NAND_BASE
+#define PISMO2_CS0_BASE PISMO2_MAP1
+#define PISMO1_ONEN_BASE ONENAND_MAP
+#define DBG_MPDB_BASE DEBUG_BASE
+
+#endif /* endif _MEM_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_H
+#define MMC_H
+
+#include "mmc_host_def.h"
+
+/* Responses */
+#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
+#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
+#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK)
+#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK)
+#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
+#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
+#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
+#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
+#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
+
+/* All supported commands */
+#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
+#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD7_DESELECT (INDEX(7)| RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
+#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
+#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE)
+#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
+#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
+#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
+#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
+
+#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16)
+#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16)
+#define MMC_DSR_DEFAULT 0x0404
+#define SD_CMD8_CHECK_PATTERN 0xAA
+#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8)
+
+/* Clock Configurations and Macros */
+
+#define MMC_CLOCK_REFERENCE 96
+#define MMC_RELATIVE_CARD_ADDRESS 0x1234
+#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80)
+#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400)
+#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1)
+#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u))
+
+#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29)
+#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29)
+#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29)
+
+#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30)
+#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30)
+#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30)
+
+#define MMC_SD2_CSD_C_SIZE_LSB_MASK 0xFFFF
+#define MMC_SD2_CSD_C_SIZE_MSB_MASK 0x003F
+#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET 16
+#define MMC_CSD_C_SIZE_LSB_MASK 0x0003
+#define MMC_CSD_C_SIZE_MSB_MASK 0x03FF
+#define MMC_CSD_C_SIZE_MSB_OFFSET 2
+
+#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0)
+#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3)
+#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0)
+#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3)
+#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3)
+
+typedef struct {
+ unsigned not_used:1;
+ unsigned crc:7;
+ unsigned ecc:2;
+ unsigned file_format:2;
+ unsigned tmp_write_protect:1;
+ unsigned perm_write_protect:1;
+ unsigned copy:1;
+ unsigned file_format_grp:1;
+ unsigned content_prot_app:1;
+ unsigned reserved_1:4;
+ unsigned write_bl_partial:1;
+ unsigned write_bl_len:4;
+ unsigned r2w_factor:3;
+ unsigned default_ecc:2;
+ unsigned wp_grp_enable:1;
+ unsigned wp_grp_size:5;
+ unsigned erase_grp_mult:5;
+ unsigned erase_grp_size:5;
+ unsigned c_size_mult:3;
+ unsigned vdd_w_curr_max:3;
+ unsigned vdd_w_curr_min:3;
+ unsigned vdd_r_curr_max:3;
+ unsigned vdd_r_curr_min:3;
+ unsigned c_size_lsb:2;
+ unsigned c_size_msb:10;
+ unsigned reserved_2:2;
+ unsigned dsr_imp:1;
+ unsigned read_blk_misalign:1;
+ unsigned write_blk_misalign:1;
+ unsigned read_bl_partial:1;
+ unsigned read_bl_len:4;
+ unsigned ccc:12;
+ unsigned tran_speed:8;
+ unsigned nsac:8;
+ unsigned taac:8;
+ unsigned reserved_3:2;
+ unsigned spec_vers:4;
+ unsigned csd_structure:2;
+} mmc_csd_reg_t;
+
+/* csd for sd2.0 */
+typedef struct {
+ unsigned not_used:1;
+ unsigned crc:7;
+ unsigned reserved_1:2;
+ unsigned file_format:2;
+ unsigned tmp_write_protect:1;
+ unsigned perm_write_protect:1;
+ unsigned copy:1;
+ unsigned file_format_grp:1;
+ unsigned reserved_2:5;
+ unsigned write_bl_partial:1;
+ unsigned write_bl_len:4;
+ unsigned r2w_factor:3;
+ unsigned reserved_3:2;
+ unsigned wp_grp_enable:1;
+ unsigned wp_grp_size:7;
+ unsigned sector_size:7;
+ unsigned erase_blk_len:1;
+ unsigned reserved_4:1;
+ unsigned c_size_lsb:16;
+ unsigned c_size_msb:6;
+ unsigned reserved_5:6;
+ unsigned dsr_imp:1;
+ unsigned read_blk_misalign:1;
+ unsigned write_blk_misalign:1;
+ unsigned read_bl_partial:1;
+ unsigned read_bl_len:4;
+ unsigned ccc:12;
+ unsigned tran_speed:8;
+ unsigned nsac:8;
+ unsigned taac:8;
+ unsigned reserved_6:6;
+ unsigned csd_structure:2;
+} mmc_sd2_csd_reg_t;
+
+/* extended csd - 512 bytes long */
+typedef struct {
+ unsigned char reserved_1[181];
+ unsigned char erasedmemorycontent;
+ unsigned char reserved_2;
+ unsigned char buswidthmode;
+ unsigned char reserved_3;
+ unsigned char highspeedinterfacetiming;
+ unsigned char reserved_4;
+ unsigned char powerclass;
+ unsigned char reserved_5;
+ unsigned char commandsetrevision;
+ unsigned char reserved_6;
+ unsigned char commandset;
+ unsigned char extendedcsdrevision;
+ unsigned char reserved_7;
+ unsigned char csdstructureversion;
+ unsigned char reserved_8;
+ unsigned char cardtype;
+ unsigned char reserved_9[3];
+ unsigned char powerclass_52mhz_1_95v;
+ unsigned char powerclass_26mhz_1_95v;
+ unsigned char powerclass_52mhz_3_6v;
+ unsigned char powerclass_26mhz_3_6v;
+ unsigned char reserved_10;
+ unsigned char minreadperf_4b_26mhz;
+ unsigned char minwriteperf_4b_26mhz;
+ unsigned char minreadperf_8b_26mhz_4b_52mhz;
+ unsigned char minwriteperf_8b_26mhz_4b_52mhz;
+ unsigned char minreadperf_8b_52mhz;
+ unsigned char minwriteperf_8b_52mhz;
+ unsigned char reserved_11;
+ unsigned int sectorcount;
+ unsigned char reserved_12[288];
+ unsigned char supportedcommandsets;
+ unsigned char reserved_13[7];
+} mmc_extended_csd_reg_t;
+
+/* mmc sd responce */
+typedef struct {
+ unsigned int ocr;
+} mmc_resp_r3;
+
+typedef struct {
+ unsigned short cardstatus;
+ unsigned short newpublishedrca;
+} mmc_resp_r6;
+
+extern mmc_card_data mmc_dev;
+
+unsigned char mmc_lowlevel_init(void);
+unsigned char mmc_send_command(unsigned int cmd, unsigned int arg,
+ unsigned int *response);
+unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd);
+unsigned char mmc_set_opendrain(unsigned char state);
+unsigned char mmc_read_data(unsigned int *output_buf);
+
+#endif /* MMC_H */
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/* T2 Register definitions */
+#define T2_BASE 0x48002000
+
+typedef struct t2 {
+ unsigned char res1[0x274];
+ unsigned int devconf0; /* 0x274 */
+ unsigned char res2[0x2A8];
+ unsigned int pbias_lite; /* 0x520 */
+} t2_t;
+
+#define MMCSDIO1ADPCLKISEL (1 << 24)
+
+#define PBIASLITEPWRDNZ0 (1 << 1)
+#define PBIASSPEEDCTRL0 (1 << 2)
+#define PBIASLITEPWRDNZ1 (1 << 9)
+
+/*
+ * OMAP HSMMC register definitions
+ */
+#define OMAP_HSMMC_BASE 0x4809C000
+
+typedef struct hsmmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned char res2[0x14];
+ unsigned int con; /* 0x2C */
+ unsigned char res3[0xD4];
+ unsigned int blk; /* 0x104 */
+ unsigned int arg; /* 0x108 */
+ unsigned int cmd; /* 0x10C */
+ unsigned int rsp10; /* 0x110 */
+ unsigned int rsp32; /* 0x114 */
+ unsigned int rsp54; /* 0x118 */
+ unsigned int rsp76; /* 0x11C */
+ unsigned int data; /* 0x120 */
+ unsigned int pstate; /* 0x124 */
+ unsigned int hctl; /* 0x128 */
+ unsigned int sysctl; /* 0x12C */
+ unsigned int stat; /* 0x130 */
+ unsigned int ie; /* 0x134 */
+ unsigned char res4[0x8];
+ unsigned int capa; /* 0x140 */
+} hsmmc_t;
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET (0x1 << 1)
+#define RESETDONE (0x1 << 0)
+#define NOOPENDRAIN (0x0 << 0)
+#define OPENDRAIN (0x1 << 0)
+#define OD (0x1 << 0)
+#define INIT_NOINIT (0x0 << 1)
+#define INIT_INITSTREAM (0x1 << 1)
+#define HR_NOHOSTRESP (0x0 << 2)
+#define STR_BLOCK (0x0 << 3)
+#define MODE_FUNC (0x0 << 4)
+#define DW8_1_4BITMODE (0x0 << 5)
+#define MIT_CTO (0x0 << 6)
+#define CDP_ACTIVEHIGH (0x0 << 7)
+#define WPP_ACTIVEHIGH (0x0 << 8)
+#define RESERVED_MASK (0x3 << 9)
+#define CTPL_MMC_SD (0x0 << 11)
+#define BLEN_512BYTESLEN (0x200 << 0)
+#define NBLK_STPCNT (0x0 << 16)
+#define DE_DISABLE (0x0 << 0)
+#define BCE_DISABLE (0x0 << 1)
+#define ACEN_DISABLE (0x0 << 2)
+#define DDIR_OFFSET (4)
+#define DDIR_MASK (0x1 << 4)
+#define DDIR_WRITE (0x0 << 4)
+#define DDIR_READ (0x1 << 4)
+#define MSBS_SGLEBLK (0x0 << 5)
+#define RSP_TYPE_OFFSET (16)
+#define RSP_TYPE_MASK (0x3 << 16)
+#define RSP_TYPE_NORSP (0x0 << 16)
+#define RSP_TYPE_LGHT136 (0x1 << 16)
+#define RSP_TYPE_LGHT48 (0x2 << 16)
+#define RSP_TYPE_LGHT48B (0x3 << 16)
+#define CCCE_NOCHECK (0x0 << 19)
+#define CCCE_CHECK (0x1 << 19)
+#define CICE_NOCHECK (0x0 << 20)
+#define CICE_CHECK (0x1 << 20)
+#define DP_OFFSET (21)
+#define DP_MASK (0x1 << 21)
+#define DP_NO_DATA (0x0 << 21)
+#define DP_DATA (0x1 << 21)
+#define CMD_TYPE_NORMAL (0x0 << 22)
+#define INDEX_OFFSET (24)
+#define INDEX_MASK (0x3f << 24)
+#define INDEX(i) (i << 24)
+#define DATI_MASK (0x1 << 1)
+#define DATI_CMDDIS (0x1 << 1)
+#define DTW_1_BITMODE (0x0 << 1)
+#define DTW_4_BITMODE (0x1 << 1)
+#define SDBP_PWROFF (0x0 << 8)
+#define SDBP_PWRON (0x1 << 8)
+#define SDVS_1V8 (0x5 << 9)
+#define SDVS_3V0 (0x6 << 9)
+#define ICE_MASK (0x1 << 0)
+#define ICE_STOP (0x0 << 0)
+#define ICS_MASK (0x1 << 1)
+#define ICS_NOTREADY (0x0 << 1)
+#define ICE_OSCILLATE (0x1 << 0)
+#define CEN_MASK (0x1 << 2)
+#define CEN_DISABLE (0x0 << 2)
+#define CEN_ENABLE (0x1 << 2)
+#define CLKD_OFFSET (6)
+#define CLKD_MASK (0x3FF << 6)
+#define DTO_MASK (0xF << 16)
+#define DTO_15THDTO (0xE << 16)
+#define SOFTRESETALL (0x1 << 24)
+#define CC_MASK (0x1 << 0)
+#define TC_MASK (0x1 << 1)
+#define BWR_MASK (0x1 << 4)
+#define BRR_MASK (0x1 << 5)
+#define ERRI_MASK (0x1 << 15)
+#define IE_CC (0x01 << 0)
+#define IE_TC (0x01 << 1)
+#define IE_BWR (0x01 << 4)
+#define IE_BRR (0x01 << 5)
+#define IE_CTO (0x01 << 16)
+#define IE_CCRC (0x01 << 17)
+#define IE_CEB (0x01 << 18)
+#define IE_CIE (0x01 << 19)
+#define IE_DTO (0x01 << 20)
+#define IE_DCRC (0x01 << 21)
+#define IE_DEB (0x01 << 22)
+#define IE_CERR (0x01 << 28)
+#define IE_BADA (0x01 << 29)
+
+#define VS30_3V0SUP (1 << 25)
+#define VS18_1V8SUP (1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE 512
+#define MMC_CARD 0
+#define SD_CARD 1
+#define BYTE_MODE 0
+#define SECTOR_MODE 1
+#define CLK_INITSEQ 0
+#define CLK_400KHZ 1
+#define CLK_MISC 2
+
+typedef struct {
+ unsigned int card_type;
+ unsigned int version;
+ unsigned int mode;
+ unsigned int size;
+ unsigned int RCA;
+} mmc_card_data;
+
+#define mmc_reg_out(addr, mask, val)\
+ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+#endif /* MMC_HOST_DEF_H */
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_H_
+#define _MUX_H_
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ */
+
+#define IEN (1 << 8)
+
+#define IDIS (0 << 8)
+#define PTU (1 << 4)
+#define PTD (0 << 4)
+#define EN (1 << 3)
+#define DIS (0 << 3)
+
+#define M0 0
+#define M1 1
+#define M2 2
+#define M3 3
+#define M4 4
+#define M5 5
+#define M6 6
+#define M7 7
+
+/*
+ * To get the actual address the offset has to added
+ * with OMAP34XX_CTRL_BASE to get the actual address
+ */
+
+/*SDRC*/
+#define CONTROL_PADCONF_SDRC_D0 0x0030
+#define CONTROL_PADCONF_SDRC_D1 0x0032
+#define CONTROL_PADCONF_SDRC_D2 0x0034
+#define CONTROL_PADCONF_SDRC_D3 0x0036
+#define CONTROL_PADCONF_SDRC_D4 0x0038
+#define CONTROL_PADCONF_SDRC_D5 0x003A
+#define CONTROL_PADCONF_SDRC_D6 0x003C
+#define CONTROL_PADCONF_SDRC_D7 0x003E
+#define CONTROL_PADCONF_SDRC_D8 0x0040
+#define CONTROL_PADCONF_SDRC_D9 0x0042
+#define CONTROL_PADCONF_SDRC_D10 0x0044
+#define CONTROL_PADCONF_SDRC_D11 0x0046
+#define CONTROL_PADCONF_SDRC_D12 0x0048
+#define CONTROL_PADCONF_SDRC_D13 0x004A
+#define CONTROL_PADCONF_SDRC_D14 0x004C
+#define CONTROL_PADCONF_SDRC_D15 0x004E
+#define CONTROL_PADCONF_SDRC_D16 0x0050
+#define CONTROL_PADCONF_SDRC_D17 0x0052
+#define CONTROL_PADCONF_SDRC_D18 0x0054
+#define CONTROL_PADCONF_SDRC_D19 0x0056
+#define CONTROL_PADCONF_SDRC_D20 0x0058
+#define CONTROL_PADCONF_SDRC_D21 0x005A
+#define CONTROL_PADCONF_SDRC_D22 0x005C
+#define CONTROL_PADCONF_SDRC_D23 0x005E
+#define CONTROL_PADCONF_SDRC_D24 0x0060
+#define CONTROL_PADCONF_SDRC_D25 0x0062
+#define CONTROL_PADCONF_SDRC_D26 0x0064
+#define CONTROL_PADCONF_SDRC_D27 0x0066
+#define CONTROL_PADCONF_SDRC_D28 0x0068
+#define CONTROL_PADCONF_SDRC_D29 0x006A
+#define CONTROL_PADCONF_SDRC_D30 0x006C
+#define CONTROL_PADCONF_SDRC_D31 0x006E
+#define CONTROL_PADCONF_SDRC_CLK 0x0070
+#define CONTROL_PADCONF_SDRC_DQS0 0x0072
+#define CONTROL_PADCONF_SDRC_DQS1 0x0074
+#define CONTROL_PADCONF_SDRC_DQS2 0x0076
+#define CONTROL_PADCONF_SDRC_DQS3 0x0078
+/*GPMC*/
+#define CONTROL_PADCONF_GPMC_A1 0x007A
+#define CONTROL_PADCONF_GPMC_A2 0x007C
+#define CONTROL_PADCONF_GPMC_A3 0x007E
+#define CONTROL_PADCONF_GPMC_A4 0x0080
+#define CONTROL_PADCONF_GPMC_A5 0x0082
+#define CONTROL_PADCONF_GPMC_A6 0x0084
+#define CONTROL_PADCONF_GPMC_A7 0x0086
+#define CONTROL_PADCONF_GPMC_A8 0x0088
+#define CONTROL_PADCONF_GPMC_A9 0x008A
+#define CONTROL_PADCONF_GPMC_A10 0x008C
+#define CONTROL_PADCONF_GPMC_D0 0x008E
+#define CONTROL_PADCONF_GPMC_D1 0x0090
+#define CONTROL_PADCONF_GPMC_D2 0x0092
+#define CONTROL_PADCONF_GPMC_D3 0x0094
+#define CONTROL_PADCONF_GPMC_D4 0x0096
+#define CONTROL_PADCONF_GPMC_D5 0x0098
+#define CONTROL_PADCONF_GPMC_D6 0x009A
+#define CONTROL_PADCONF_GPMC_D7 0x009C
+#define CONTROL_PADCONF_GPMC_D8 0x009E
+#define CONTROL_PADCONF_GPMC_D9 0x00A0
+#define CONTROL_PADCONF_GPMC_D10 0x00A2
+#define CONTROL_PADCONF_GPMC_D11 0x00A4
+#define CONTROL_PADCONF_GPMC_D12 0x00A6
+#define CONTROL_PADCONF_GPMC_D13 0x00A8
+#define CONTROL_PADCONF_GPMC_D14 0x00AA
+#define CONTROL_PADCONF_GPMC_D15 0x00AC
+#define CONTROL_PADCONF_GPMC_NCS0 0x00AE
+#define CONTROL_PADCONF_GPMC_NCS1 0x00B0
+#define CONTROL_PADCONF_GPMC_NCS2 0x00B2
+#define CONTROL_PADCONF_GPMC_NCS3 0x00B4
+#define CONTROL_PADCONF_GPMC_NCS4 0x00B6
+#define CONTROL_PADCONF_GPMC_NCS5 0x00B8
+#define CONTROL_PADCONF_GPMC_NCS6 0x00BA
+#define CONTROL_PADCONF_GPMC_NCS7 0x00BC
+#define CONTROL_PADCONF_GPMC_CLK 0x00BE
+#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0
+#define CONTROL_PADCONF_GPMC_NOE 0x00C2
+#define CONTROL_PADCONF_GPMC_NWE 0x00C4
+#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6
+#define CONTROL_PADCONF_GPMC_NBE1 0x00C8
+#define CONTROL_PADCONF_GPMC_NWP 0x00CA
+#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC
+#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE
+#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0
+#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2
+/*DSS*/
+#define CONTROL_PADCONF_DSS_PCLK 0x00D4
+#define CONTROL_PADCONF_DSS_HSYNC 0x00D6
+#define CONTROL_PADCONF_DSS_VSYNC 0x00D8
+#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA
+#define CONTROL_PADCONF_DSS_DATA0 0x00DC
+#define CONTROL_PADCONF_DSS_DATA1 0x00DE
+#define CONTROL_PADCONF_DSS_DATA2 0x00E0
+#define CONTROL_PADCONF_DSS_DATA3 0x00E2
+#define CONTROL_PADCONF_DSS_DATA4 0x00E4
+#define CONTROL_PADCONF_DSS_DATA5 0x00E6
+#define CONTROL_PADCONF_DSS_DATA6 0x00E8
+#define CONTROL_PADCONF_DSS_DATA7 0x00EA
+#define CONTROL_PADCONF_DSS_DATA8 0x00EC
+#define CONTROL_PADCONF_DSS_DATA9 0x00EE
+#define CONTROL_PADCONF_DSS_DATA10 0x00F0
+#define CONTROL_PADCONF_DSS_DATA11 0x00F2
+#define CONTROL_PADCONF_DSS_DATA12 0x00F4
+#define CONTROL_PADCONF_DSS_DATA13 0x00F6
+#define CONTROL_PADCONF_DSS_DATA14 0x00F8
+#define CONTROL_PADCONF_DSS_DATA15 0x00FA
+#define CONTROL_PADCONF_DSS_DATA16 0x00FC
+#define CONTROL_PADCONF_DSS_DATA17 0x00FE
+#define CONTROL_PADCONF_DSS_DATA18 0x0100
+#define CONTROL_PADCONF_DSS_DATA19 0x0102
+#define CONTROL_PADCONF_DSS_DATA20 0x0104
+#define CONTROL_PADCONF_DSS_DATA21 0x0106
+#define CONTROL_PADCONF_DSS_DATA22 0x0108
+#define CONTROL_PADCONF_DSS_DATA23 0x010A
+/*CAMERA*/
+#define CONTROL_PADCONF_CAM_HS 0x010C
+#define CONTROL_PADCONF_CAM_VS 0x010E
+#define CONTROL_PADCONF_CAM_XCLKA 0x0110
+#define CONTROL_PADCONF_CAM_PCLK 0x0112
+#define CONTROL_PADCONF_CAM_FLD 0x0114
+#define CONTROL_PADCONF_CAM_D0 0x0116
+#define CONTROL_PADCONF_CAM_D1 0x0118
+#define CONTROL_PADCONF_CAM_D2 0x011A
+#define CONTROL_PADCONF_CAM_D3 0x011C
+#define CONTROL_PADCONF_CAM_D4 0x011E
+#define CONTROL_PADCONF_CAM_D5 0x0120
+#define CONTROL_PADCONF_CAM_D6 0x0122
+#define CONTROL_PADCONF_CAM_D7 0x0124
+#define CONTROL_PADCONF_CAM_D8 0x0126
+#define CONTROL_PADCONF_CAM_D9 0x0128
+#define CONTROL_PADCONF_CAM_D10 0x012A
+#define CONTROL_PADCONF_CAM_D11 0x012C
+#define CONTROL_PADCONF_CAM_XCLKB 0x012E
+#define CONTROL_PADCONF_CAM_WEN 0x0130
+#define CONTROL_PADCONF_CAM_STROBE 0x0132
+#define CONTROL_PADCONF_CSI2_DX0 0x0134
+#define CONTROL_PADCONF_CSI2_DY0 0x0136
+#define CONTROL_PADCONF_CSI2_DX1 0x0138
+#define CONTROL_PADCONF_CSI2_DY1 0x013A
+/*Audio Interface */
+#define CONTROL_PADCONF_MCBSP2_FSX 0x013C
+#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E
+#define CONTROL_PADCONF_MCBSP2_DR 0x0140
+#define CONTROL_PADCONF_MCBSP2_DX 0x0142
+#define CONTROL_PADCONF_MMC1_CLK 0x0144
+#define CONTROL_PADCONF_MMC1_CMD 0x0146
+#define CONTROL_PADCONF_MMC1_DAT0 0x0148
+#define CONTROL_PADCONF_MMC1_DAT1 0x014A
+#define CONTROL_PADCONF_MMC1_DAT2 0x014C
+#define CONTROL_PADCONF_MMC1_DAT3 0x014E
+#define CONTROL_PADCONF_MMC1_DAT4 0x0150
+#define CONTROL_PADCONF_MMC1_DAT5 0x0152
+#define CONTROL_PADCONF_MMC1_DAT6 0x0154
+#define CONTROL_PADCONF_MMC1_DAT7 0x0156
+/*Wireless LAN */
+#define CONTROL_PADCONF_MMC2_CLK 0x0158
+#define CONTROL_PADCONF_MMC2_CMD 0x015A
+#define CONTROL_PADCONF_MMC2_DAT0 0x015C
+#define CONTROL_PADCONF_MMC2_DAT1 0x015E
+#define CONTROL_PADCONF_MMC2_DAT2 0x0160
+#define CONTROL_PADCONF_MMC2_DAT3 0x0162
+#define CONTROL_PADCONF_MMC2_DAT4 0x0164
+#define CONTROL_PADCONF_MMC2_DAT5 0x0166
+#define CONTROL_PADCONF_MMC2_DAT6 0x0168
+#define CONTROL_PADCONF_MMC2_DAT7 0x016A
+/*Bluetooth*/
+#define CONTROL_PADCONF_MCBSP3_DX 0x016C
+#define CONTROL_PADCONF_MCBSP3_DR 0x016E
+#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170
+#define CONTROL_PADCONF_MCBSP3_FSX 0x0172
+#define CONTROL_PADCONF_UART2_CTS 0x0174
+#define CONTROL_PADCONF_UART2_RTS 0x0176
+#define CONTROL_PADCONF_UART2_TX 0x0178
+#define CONTROL_PADCONF_UART2_RX 0x017A
+/*Modem Interface */
+#define CONTROL_PADCONF_UART1_TX 0x017C
+#define CONTROL_PADCONF_UART1_RTS 0x017E
+#define CONTROL_PADCONF_UART1_CTS 0x0180
+#define CONTROL_PADCONF_UART1_RX 0x0182
+#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184
+#define CONTROL_PADCONF_MCBSP4_DR 0x0186
+#define CONTROL_PADCONF_MCBSP4_DX 0x0188
+#define CONTROL_PADCONF_MCBSP4_FSX 0x018A
+#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C
+#define CONTROL_PADCONF_MCBSP1_FSR 0x018E
+#define CONTROL_PADCONF_MCBSP1_DX 0x0190
+#define CONTROL_PADCONF_MCBSP1_DR 0x0192
+#define CONTROL_PADCONF_MCBSP_CLKS 0x0194
+#define CONTROL_PADCONF_MCBSP1_FSX 0x0196
+#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198
+/*Serial Interface*/
+#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A
+#define CONTROL_PADCONF_UART3_RTS_SD 0x019C
+#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E
+#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0
+#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2
+#define CONTROL_PADCONF_HSUSB0_STP 0x01A4
+#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6
+#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8
+#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA
+#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC
+#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE
+#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0
+#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2
+#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4
+#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6
+#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8
+#define CONTROL_PADCONF_I2C1_SCL 0x01BA
+#define CONTROL_PADCONF_I2C1_SDA 0x01BC
+#define CONTROL_PADCONF_I2C2_SCL 0x01BE
+#define CONTROL_PADCONF_I2C2_SDA 0x01C0
+#define CONTROL_PADCONF_I2C3_SCL 0x01C2
+#define CONTROL_PADCONF_I2C3_SDA 0x01C4
+#define CONTROL_PADCONF_I2C4_SCL 0x0A00
+#define CONTROL_PADCONF_I2C4_SDA 0x0A02
+#define CONTROL_PADCONF_HDQ_SIO 0x01C6
+#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8
+#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA
+#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC
+#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE
+#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0
+#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2
+#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4
+#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6
+#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8
+#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA
+#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC
+#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE
+/*Control and debug */
+#define CONTROL_PADCONF_SYS_32K 0x0A04
+#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06
+#define CONTROL_PADCONF_SYS_NIRQ 0x01E0
+#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A
+#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C
+#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E
+#define CONTROL_PADCONF_SYS_BOOT3 0x0A10
+#define CONTROL_PADCONF_SYS_BOOT4 0x0A12
+#define CONTROL_PADCONF_SYS_BOOT5 0x0A14
+#define CONTROL_PADCONF_SYS_BOOT6 0x0A16
+#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
+#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
+#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
+#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C
+#define CONTROL_PADCONF_JTAG_TCK 0x0A1E
+#define CONTROL_PADCONF_JTAG_TMS 0x0A20
+#define CONTROL_PADCONF_JTAG_TDI 0x0A22
+#define CONTROL_PADCONF_JTAG_EMU0 0x0A24
+#define CONTROL_PADCONF_JTAG_EMU1 0x0A26
+#define CONTROL_PADCONF_ETK_CLK 0x0A28
+#define CONTROL_PADCONF_ETK_CTL 0x0A2A
+#define CONTROL_PADCONF_ETK_D0 0x0A2C
+#define CONTROL_PADCONF_ETK_D1 0x0A2E
+#define CONTROL_PADCONF_ETK_D2 0x0A30
+#define CONTROL_PADCONF_ETK_D3 0x0A32
+#define CONTROL_PADCONF_ETK_D4 0x0A34
+#define CONTROL_PADCONF_ETK_D5 0x0A36
+#define CONTROL_PADCONF_ETK_D6 0x0A38
+#define CONTROL_PADCONF_ETK_D7 0x0A3A
+#define CONTROL_PADCONF_ETK_D8 0x0A3C
+#define CONTROL_PADCONF_ETK_D9 0x0A3E
+#define CONTROL_PADCONF_ETK_D10 0x0A40
+#define CONTROL_PADCONF_ETK_D11 0x0A42
+#define CONTROL_PADCONF_ETK_D12 0x0A44
+#define CONTROL_PADCONF_ETK_D13 0x0A46
+#define CONTROL_PADCONF_ETK_D14 0x0A48
+#define CONTROL_PADCONF_ETK_D15 0x0A4A
+#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8
+#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA
+#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC
+#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE
+#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0
+#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2
+#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4
+#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6
+#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8
+#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA
+#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC
+#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE
+#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0
+#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2
+#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4
+#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
+#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
+#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
+/*Die to Die */
+#define CONTROL_PADCONF_D2D_MCAD0 0x01E4
+#define CONTROL_PADCONF_D2D_MCAD1 0x01E6
+#define CONTROL_PADCONF_D2D_MCAD2 0x01E8
+#define CONTROL_PADCONF_D2D_MCAD3 0x01EA
+#define CONTROL_PADCONF_D2D_MCAD4 0x01EC
+#define CONTROL_PADCONF_D2D_MCAD5 0x01EE
+#define CONTROL_PADCONF_D2D_MCAD6 0x01F0
+#define CONTROL_PADCONF_D2D_MCAD7 0x01F2
+#define CONTROL_PADCONF_D2D_MCAD8 0x01F4
+#define CONTROL_PADCONF_D2D_MCAD9 0x01F6
+#define CONTROL_PADCONF_D2D_MCAD10 0x01F8
+#define CONTROL_PADCONF_D2D_MCAD11 0x01FA
+#define CONTROL_PADCONF_D2D_MCAD12 0x01FC
+#define CONTROL_PADCONF_D2D_MCAD13 0x01FE
+#define CONTROL_PADCONF_D2D_MCAD14 0x0200
+#define CONTROL_PADCONF_D2D_MCAD15 0x0202
+#define CONTROL_PADCONF_D2D_MCAD16 0x0204
+#define CONTROL_PADCONF_D2D_MCAD17 0x0206
+#define CONTROL_PADCONF_D2D_MCAD18 0x0208
+#define CONTROL_PADCONF_D2D_MCAD19 0x020A
+#define CONTROL_PADCONF_D2D_MCAD20 0x020C
+#define CONTROL_PADCONF_D2D_MCAD21 0x020E
+#define CONTROL_PADCONF_D2D_MCAD22 0x0210
+#define CONTROL_PADCONF_D2D_MCAD23 0x0212
+#define CONTROL_PADCONF_D2D_MCAD24 0x0214
+#define CONTROL_PADCONF_D2D_MCAD25 0x0216
+#define CONTROL_PADCONF_D2D_MCAD26 0x0218
+#define CONTROL_PADCONF_D2D_MCAD27 0x021A
+#define CONTROL_PADCONF_D2D_MCAD28 0x021C
+#define CONTROL_PADCONF_D2D_MCAD29 0x021E
+#define CONTROL_PADCONF_D2D_MCAD30 0x0220
+#define CONTROL_PADCONF_D2D_MCAD31 0x0222
+#define CONTROL_PADCONF_D2D_MCAD32 0x0224
+#define CONTROL_PADCONF_D2D_MCAD33 0x0226
+#define CONTROL_PADCONF_D2D_MCAD34 0x0228
+#define CONTROL_PADCONF_D2D_MCAD35 0x022A
+#define CONTROL_PADCONF_D2D_MCAD36 0x022C
+#define CONTROL_PADCONF_D2D_CLK26MI 0x022E
+#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230
+#define CONTROL_PADCONF_D2D_NRESWARM 0x0232
+#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234
+#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236
+#define CONTROL_PADCONF_D2D_SPINT 0x0238
+#define CONTROL_PADCONF_D2D_FRINT 0x023A
+#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C
+#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E
+#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240
+#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242
+#define CONTROL_PADCONF_D2D_N3GTRST 0x0244
+#define CONTROL_PADCONF_D2D_N3GTDI 0x0246
+#define CONTROL_PADCONF_D2D_N3GTDO 0x0248
+#define CONTROL_PADCONF_D2D_N3GTMS 0x024A
+#define CONTROL_PADCONF_D2D_N3GTCK 0x024C
+#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E
+#define CONTROL_PADCONF_D2D_MSTDBY 0x0250
+#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C
+#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252
+#define CONTROL_PADCONF_D2D_IDLEACK 0x0254
+#define CONTROL_PADCONF_D2D_MWRITE 0x0256
+#define CONTROL_PADCONF_D2D_SWRITE 0x0258
+#define CONTROL_PADCONF_D2D_MREAD 0x025A
+#define CONTROL_PADCONF_D2D_SREAD 0x025C
+#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E
+#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260
+#define CONTROL_PADCONF_SDRC_CKE0 0x0262
+#define CONTROL_PADCONF_SDRC_CKE1 0x0264
+
+#define MUX_VAL(OFFSET,VALUE)\
+ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+
+#define CP(x) (CONTROL_PADCONF_##x)
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_OMAP_GPMC_H
+#define __ASM_ARCH_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY 0
+#define GPMC_BUF_FULL 1
+
+#define ECCCLEAR (0x1 << 8)
+#define ECCRESULTREG1 (0x1 << 0)
+#define ECCSIZE512BYTE 0xFF
+#define ECCSIZE1 (ECCSIZE512BYTE << 22)
+#define ECCSIZE0 (ECCSIZE512BYTE << 12)
+#define ECCSIZE0SEL (0x000 << 0)
+
+/* Generic ECC Layouts */
+/* Large Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 12,\
+ .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
+ 9, 10, 11, 12},\
+ .oobfree = {\
+ {.offset = 13,\
+ .length = 51 } } \
+}
+#endif
+
+/* Large Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 12,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13},\
+ .oobfree = {\
+ {.offset = 14,\
+ .length = 50 } } \
+}
+#endif
+
+/* Small Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 3,\
+ .eccpos = {1, 2, 3},\
+ .oobfree = {\
+ {.offset = 4,\
+ .length = 12 } } \
+}
+#endif
+
+/* Small Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 3,\
+ .eccpos = {2, 3, 4},\
+ .oobfree = {\
+ {.offset = 5,\
+ .length = 11 } } \
+}
+#endif
+
+#endif /* __ASM_ARCH_OMAP_GPMC_H */
--- /dev/null
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+typedef struct {
+ u32 mtype;
+ char *board_string;
+ char *nand_string;
+} omap3_sysinfo;
+
+void prcm_init(void);
+void per_clocks_enable(void);
+
+void memif_init(void);
+void sdrc_init(void);
+void do_sdrc_init(u32, u32);
+void gpmc_init(void);
+
+void watchdog_init(void);
+void set_muxconf_regs(void);
+
+u32 get_cpu_rev(void);
+u32 get_mem_type(void);
+u32 get_sysboot_value(void);
+u32 is_gpmc_muxed(void);
+u32 get_gpmc0_type(void);
+u32 get_gpmc0_width(void);
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+u32 is_running_in_sdram(void);
+u32 is_running_in_sram(void);
+u32 is_running_in_flash(void);
+u32 get_device_type(void);
+void l2cache_enable(void);
+void secureworld_exit(void);
+void setup_auxcr(void);
+void try_unlock_memory(void);
+u32 get_boot_type(void);
+void v7_flush_dcache_all(u32);
+void sr32(void *, u32, u32, u32);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void make_cs1_contiguous(void);
+void omap_nand_switch_ecc(int);
+void power_init_r(void);
+void dieid_num_r(void);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TT_H_
+#define _TT_H_
+
+/* Stuff on L3 Interconnect */
+#define SMX_APE_BASE 0x68000000
+
+/* GPMC */
+#define OMAP34XX_GPMC_BASE 0x6E000000
+
+/* SMS */
+#define OMAP34XX_SMS_BASE 0x6C000000
+
+/* SDRC */
+#define OMAP34XX_SDRC_BASE 0x6D000000
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
+#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
+#define OMAP34XX_ID_L4_IO_BASE 0x4830A200
+#define OMAP34XX_L4_PER 0x49000000
+#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
+
+/* CONTROL */
+#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
+
+/* UART */
+#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
+#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
+#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
+
+/* General Purpose Timers */
+#define OMAP34XX_GPT1 0x48318000
+#define OMAP34XX_GPT2 0x49032000
+#define OMAP34XX_GPT3 0x49034000
+#define OMAP34XX_GPT4 0x49036000
+#define OMAP34XX_GPT5 0x49038000
+#define OMAP34XX_GPT6 0x4903A000
+#define OMAP34XX_GPT7 0x4903C000
+#define OMAP34XX_GPT8 0x4903E000
+#define OMAP34XX_GPT9 0x49040000
+#define OMAP34XX_GPT10 0x48086000
+#define OMAP34XX_GPT11 0x48088000
+#define OMAP34XX_GPT12 0x48304000
+
+/* WatchDog Timers (1 secure, 3 GP) */
+#define WD1_BASE 0x4830C000
+#define WD2_BASE 0x48314000
+#define WD3_BASE 0x49030000
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE 0x48320000
+
+#ifndef __ASSEMBLY__
+
+typedef struct s32ktimer {
+ unsigned char res[0x10];
+ unsigned int s32k_cr; /* 0x10 */
+} s32ktimer_t;
+
+#endif /* __ASSEMBLY__ */
+
+/* OMAP3 GPIO registers */
+#define OMAP34XX_GPIO1_BASE 0x48310000
+#define OMAP34XX_GPIO2_BASE 0x49050000
+#define OMAP34XX_GPIO3_BASE 0x49052000
+#define OMAP34XX_GPIO4_BASE 0x49054000
+#define OMAP34XX_GPIO5_BASE 0x49056000
+#define OMAP34XX_GPIO6_BASE 0x49058000
+
+#ifndef __ASSEMBLY__
+typedef struct gpio {
+ unsigned char res1[0x34];
+ unsigned int oe; /* 0x34 */
+ unsigned int datain; /* 0x38 */
+ unsigned char res2[0x54];
+ unsigned int cleardataout; /* 0x90 */
+ unsigned int setdataout; /* 0x94 */
+} gpio_t;
+#endif /* __ASSEMBLY__ */
+
+#define GPIO0 (0x1 << 0)
+#define GPIO1 (0x1 << 1)
+#define GPIO2 (0x1 << 2)
+#define GPIO3 (0x1 << 3)
+#define GPIO4 (0x1 << 4)
+#define GPIO5 (0x1 << 5)
+#define GPIO6 (0x1 << 6)
+#define GPIO7 (0x1 << 7)
+#define GPIO8 (0x1 << 8)
+#define GPIO9 (0x1 << 9)
+#define GPIO10 (0x1 << 10)
+#define GPIO11 (0x1 << 11)
+#define GPIO12 (0x1 << 12)
+#define GPIO13 (0x1 << 13)
+#define GPIO14 (0x1 << 14)
+#define GPIO15 (0x1 << 15)
+#define GPIO16 (0x1 << 16)
+#define GPIO17 (0x1 << 17)
+#define GPIO18 (0x1 << 18)
+#define GPIO19 (0x1 << 19)
+#define GPIO20 (0x1 << 20)
+#define GPIO21 (0x1 << 21)
+#define GPIO22 (0x1 << 22)
+#define GPIO23 (0x1 << 23)
+#define GPIO24 (0x1 << 24)
+#define GPIO25 (0x1 << 25)
+#define GPIO26 (0x1 << 26)
+#define GPIO27 (0x1 << 27)
+#define GPIO28 (0x1 << 28)
+#define GPIO29 (0x1 << 29)
+#define GPIO30 (0x1 << 30)
+#define GPIO31 (0x1 << 31)
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0 0x40000000
+#define SRAM_OFFSET1 0x00200000
+#define SRAM_OFFSET2 0x0000F800
+#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
+ SRAM_OFFSET2)
+
+#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
+
+#define DEBUG_LED1 149 /* gpio */
+#define DEBUG_LED2 150 /* gpio */
+
+#define XDR_POP 5 /* package on package part */
+#define SDR_DISCRETE 4 /* 128M memory SDR module */
+#define DDR_STACKED 3 /* stacked part on 2422 */
+#define DDR_COMBO 2 /* combo part on cpu daughter card */
+#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
+
+#define DDR_100 100 /* type found on most mem d-boards */
+#define DDR_111 111 /* some combo parts */
+#define DDR_133 133 /* most combo, some mem d-boards */
+#define DDR_165 165 /* future parts */
+
+#define CPU_3430 0x3430
+
+/*
+ * 343x real hardware:
+ * ES1 = rev 0
+ *
+ * ES2 onwards, the value maps to contents of IDCODE register [31:28].
+ */
+#define CPU_3XX_ES10 0
+#define CPU_3XX_ES20 1
+#define CPU_3XX_ES21 2
+#define CPU_3XX_ES30 3
+#define CPU_3XX_ES31 4
+#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1)
+
+#define CPU_3XX_ID_SHIFT 28
+
+#define WIDTH_8BIT 0x0000
+#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
+
+/* I2C power management companion definitions */
+#define PWRMGT_ADDR_ID1 0x48
+#define PWRMGT_ADDR_ID2 0x49
+#define PWRMGT_ADDR_ID3 0x4A
+#define PWRMGT_ADDR_ID4 0x4B
+
+/* I2C ID3 (slave3) register */
+#define LEDEN 0xEE
+
+#define LEDAON (0x1 << 0)
+#define LEDBON (0x1 << 1)
+#define LEDAPWM (0x1 << 4)
+#define LEDBPWM (0x1 << 5)
+
+/* I2C ID4 (slave4) register */
+#define VAUX2_DEV_GRP 0x76
+#define VAUX2_DEDICATED 0x79
+#define VAUX3_DEV_GRP 0x7A
+#define VAUX3_DEDICATED 0x7D
+#define VMMC1_DEV_GRP 0x82
+#define VMMC1_DEDICATED 0x85
+#define VPLL2_DEV_GRP 0x8E
+#define VPLL2_DEDICATED 0x91
+#define VDAC_DEV_GRP 0x96
+#define VDAC_DEDICATED 0x99
+
+#define DEV_GRP_P1 0x20
+#define DEV_GRP_ALL 0xE0
+
+#define VAUX2_VSEL_28 0x09
+#define VAUX3_VSEL_28 0x03
+#define VPLL2_VSEL_18 0x05
+#define VDAC_VSEL_18 0x03
+#define VMMC1_VSEL_30 0x02
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
+#define CONFIG_S5PC100 1 /* which is in a S5PC100 */
+#define CONFIG_S5PC100_TT 1 /* working with TT */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/tt.h>
+
+#define CONFIG_SYS_SDRAM_BASE 0x50000000
+
+/* input clock of PLL: SMDK6400 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+
+#define CONFIG_MEMORY_UPPER_CODE
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+/*
+ * Architecture magic and machine type
+ */
+#define MACH_TYPE 1270
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
+#define CS8900_BASE 0x18800300
+#define CS8900_BUS16 1 /* follow the Linux driver */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */
+
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#define CONFIG_CMDLINE_EDITING
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_NAND
+#if defined(CONFIG_BOOT_ONENAND)
+#define CONFIG_CMD_ONENAND
+#endif
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "SMDK6400 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */
+
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+
+#define CONFIG_SYS_HZ 1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */
+
+/**********************************
+ Support Clock Settings
+ **********************************
+ Setting SYNC ASYNC
+ ----------------------------------
+ 667_133_66 X O
+ 533_133_66 O O
+ 400_133_66 X O
+ 400_100_50 O O
+ **********************************/
+
+/*#define CONFIG_CLK_667_133_66*/
+#define CONFIG_CLK_533_133_66
+/*
+#define CONFIG_CLK_400_100_50
+#define CONFIG_CLK_400_133_66
+#define CONFIG_SYNC_MODE
+*/
+
+/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */
+
+#define CONFIG_SYS_FLASH_BASE 0x10000000
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+/* AM29LV160B has 35 sectors, AM29LV800B - 19 */
+#define CONFIG_SYS_MAX_FLASH_SECT 40
+
+//#define CONFIG_SYS_NO_FLASH 1
+
+#define CONFIG_AMD_LV800
+#define CONFIG_SYS_FLASH_CFI 1 /* Use CFI parameters (needed?) */
+/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
+
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/*
+ * SMDK6400 board specific data
+ */
+
+#define CONFIG_IDENT_STRING " for SMDK6400"
+
+/* base address for uboot */
+#define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x07e00000)
+/* total memory available to uboot */
+#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024)
+
+#ifdef CONFIG_ENABLE_MMU
+#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
+#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \
+ "bootm 0xc0018000"
+#else
+#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \
+ "bootm 0x50018000"
+#endif
+
+/* NAND U-Boot load and start address */
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000)
+
+#define CONFIG_ENV_OFFSET 0x0040000
+
+/* NAND configuration */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x70200010
+#define CONFIG_SYS_S3C_NAND_HWECC
+
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CONFIG_SYS_NAND_WP 1
+#define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */
+#define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */
+
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */
+
+/* NAND chip page size */
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+/* NAND chip block size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+/* NAND chip page per block count */
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+/* Location of the bad-block label */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+/* Extra address cycle for > 128MiB */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
+#define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE
+/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
+#define CONFIG_SYS_NAND_ECCBYTES 4
+/* Number of ECC-blocks per NAND page */
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+/* Size of a single OOB region */
+#define CONFIG_SYS_NAND_OOBSIZE 64
+/* Number of ECC bytes per page */
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
+/* ECC byte positions */
+#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
+ 48, 49, 50, 51, 52, 53, 54, 55, \
+ 56, 57, 58, 59, 60, 61, 62, 63}
+
+/* Boot configuration (define only one of next 3) */
+#define CONFIG_BOOT_NAND
+/* None of these are currently implemented. Left from the original Samsung
+ * version for reference
+#define CONFIG_BOOT_NOR
+#define CONFIG_BOOT_MOVINAND
+#define CONFIG_BOOT_ONENAND
+*/
+
+#define CONFIG_NAND
+#define CONFIG_NAND_S3C64XX
+/* Unimplemented or unsupported. See comment above.
+#define CONFIG_ONENAND
+#define CONFIG_MOVINAND
+*/
+
+/* Settings as above boot configuration */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_BOOTARGS "console=ttySAC,115200"
+
+#if !defined(CONFIG_ENABLE_MMU)
+#define CONFIG_CMD_USB 1
+#define CONFIG_USB_S3C64XX
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+
+#define CONFIG_USB_STORAGE 1
+#endif
+#define CONFIG_DOS_PARTITION 1
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU)
+# error "usb_ohci.c is currently broken with MMU enabled."
+#endif
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : S3C64XX.h
+ * Version : 31.3.2003
+ *
+ * common stuff for SAMSUNG S3C64XX SoC
+ ************************************************/
+
+#ifndef __S3C64XX_H__
+#define __S3C64XX_H__
+
+#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S5PC100)
+#error CONFIG_SYNC_MODE unavailable on S5PC100, please, fix your configuration!
+#endif
+
+#include <asm/types.h>
+
+/* UART (see manual chapter 11) */
+typedef struct {
+ volatile u32 ULCON;
+ volatile u32 UCON;
+ volatile u32 UFCON;
+ volatile u32 UMCON;
+ volatile u32 UTRSTAT;
+ volatile u32 UERSTAT;
+ volatile u32 UFSTAT;
+ volatile u32 UMSTAT;
+#ifdef __BIG_ENDIAN
+ volatile u8 res1[3];
+ volatile u8 UTXH;
+ volatile u8 res2[3];
+ volatile u8 URXH;
+#else /* Little Endian */
+ volatile u8 UTXH;
+ volatile u8 res1[3];
+ volatile u8 URXH;
+ volatile u8 res2[3];
+#endif
+ volatile u32 UBRDIV;
+#ifdef __BIG_ENDIAN
+ volatile u8 res3[2];
+ volatile u16 UDIVSLOT;
+#else
+ volatile u16 UDIVSLOT;
+ volatile u8 res3[2];
+#endif
+} s3c64xx_uart;
+
+/* PWM TIMER (see manual chapter 10) */
+typedef struct {
+ volatile u32 TCNTB;
+ volatile u32 TCMPB;
+ volatile u32 TCNTO;
+} s3c64xx_timer;
+
+typedef struct {
+ volatile u32 TCFG0;
+ volatile u32 TCFG1;
+ volatile u32 TCON;
+ s3c64xx_timer ch[4];
+ volatile u32 TCNTB4;
+ volatile u32 TCNTO4;
+} s3c64xx_timers;
+
+#endif /*__S3C64XX_H__*/
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
+ * - only support for S3C6400
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c6400.h
+ *
+ * Based on S3C6400 User's manual Rev 0.0
+ ************************************************/
+
+#ifndef __S3C6400_H__
+#define __S3C6400_H__
+
+#define S3C64XX_UART_CHANNELS 3
+#define S3C64XX_SPI_CHANNELS 2
+
+#include <asm/hardware.h>
+
+#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
+
+/* Clock & Power Controller for mDirac3*/
+#define APLL_LOCK_OFFSET 0x00
+#define MPLL_LOCK_OFFSET 0x04
+#define EPLL_LOCK_OFFSET 0x08
+#define APLL_CON_OFFSET 0x0C
+#define MPLL_CON_OFFSET 0x10
+#define EPLL_CON0_OFFSET 0x14
+#define EPLL_CON1_OFFSET 0x18
+#define CLK_SRC_OFFSET 0x1C
+#define CLK_DIV0_OFFSET 0x20
+#define CLK_DIV1_OFFSET 0x24
+#define CLK_DIV2_OFFSET 0x28
+#define CLK_OUT_OFFSET 0x2C
+#define HCLK_GATE_OFFSET 0x30
+#define PCLK_GATE_OFFSET 0x34
+#define SCLK_GATE_OFFSET 0x38
+#define AHB_CON0_OFFSET 0x100
+#define AHB_CON1_OFFSET 0x104
+#define AHB_CON2_OFFSET 0x108
+#define SELECT_DMA_OFFSET 0x110
+#define SW_RST_OFFSET 0x114
+#define SYS_ID_OFFSET 0x118
+#define MEM_SYS_CFG_OFFSET 0x120
+#define QOS_OVERRIDE0_OFFSET 0x124
+#define QOS_OVERRIDE1_OFFSET 0x128
+#define MEM_CFG_STAT_OFFSET 0x12C
+#define PWR_CFG_OFFSET 0x804
+#define EINT_MASK_OFFSET 0x808
+#define NOR_CFG_OFFSET 0x810
+#define STOP_CFG_OFFSET 0x814
+#define SLEEP_CFG_OFFSET 0x818
+#define OSC_FREQ_OFFSET 0x820
+#define OSC_STABLE_OFFSET 0x824
+#define PWR_STABLE_OFFSET 0x828
+#define FPC_STABLE_OFFSET 0x82C
+#define MTC_STABLE_OFFSET 0x830
+#define OTHERS_OFFSET 0x900
+#define RST_STAT_OFFSET 0x904
+#define WAKEUP_STAT_OFFSET 0x908
+#define BLK_PWR_STAT_OFFSET 0x90C
+#define INF_REG0_OFFSET 0xA00
+#define INF_REG1_OFFSET 0xA04
+#define INF_REG2_OFFSET 0xA08
+#define INF_REG3_OFFSET 0xA0C
+#define INF_REG4_OFFSET 0xA10
+#define INF_REG5_OFFSET 0xA14
+#define INF_REG6_OFFSET 0xA18
+#define INF_REG7_OFFSET 0xA1C
+
+#define OSC_CNT_VAL_OFFSET 0x824
+#define PWR_CNT_VAL_OFFSET 0x828
+#define FPC_CNT_VAL_OFFSET 0x82C
+#define MTC_CNT_VAL_OFFSET 0x830
+
+#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
+#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
+#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
+#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
+#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
+#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
+#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
+#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
+#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
+#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
+#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
+#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
+#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
+#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
+#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
+#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
+#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
+#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
+#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ SELECT_DMA_OFFSET)
+#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
+#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
+#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ MEM_SYS_CFG_OFFSET)
+#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ QOS_OVERRIDE0_OFFSET)
+#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ QOS_OVERRIDE1_OFFSET)
+#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ MEM_CFG_STAT_OFFSET)
+#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
+#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
+#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
+#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
+#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
+#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
+#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ OSC_CNT_VAL_OFFSET)
+#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ PWR_CNT_VAL_OFFSET)
+#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ FPC_CNT_VAL_OFFSET)
+#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ MTC_CNT_VAL_OFFSET)
+#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
+#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
+#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ WAKEUP_STAT_OFFSET)
+#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
+ BLK_PWR_STAT_OFFSET)
+#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
+#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
+#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
+#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
+#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
+#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
+#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
+#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
+
+#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
+#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
+#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
+#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
+#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
+#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
+#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
+#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
+#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
+#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
+#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
+#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
+#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
+#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
+#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
+#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
+#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
+#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
+#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
+#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
+#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
+#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET)
+#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
+#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
+#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
+#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
+#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
+#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
+#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
+#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
+#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
+#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
+#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
+#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
+#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
+#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
+#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
+#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
+#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
+#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
+#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
+#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
+#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
+#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
+#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
+#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
+#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
+
+
+/*
+ * GPIO
+ */
+#define ELFIN_GPIO_BASE 0x7f008000
+
+#define GPACON_OFFSET 0x00
+#define GPADAT_OFFSET 0x04
+#define GPAPUD_OFFSET 0x08
+#define GPACONSLP_OFFSET 0x0C
+#define GPAPUDSLP_OFFSET 0x10
+#define GPBCON_OFFSET 0x20
+#define GPBDAT_OFFSET 0x24
+#define GPBPUD_OFFSET 0x28
+#define GPBCONSLP_OFFSET 0x2C
+#define GPBPUDSLP_OFFSET 0x30
+#define GPCCON_OFFSET 0x40
+#define GPCDAT_OFFSET 0x44
+#define GPCPUD_OFFSET 0x48
+#define GPCCONSLP_OFFSET 0x4C
+#define GPCPUDSLP_OFFSET 0x50
+#define GPDCON_OFFSET 0x60
+#define GPDDAT_OFFSET 0x64
+#define GPDPUD_OFFSET 0x68
+#define GPDCONSLP_OFFSET 0x6C
+#define GPDPUDSLP_OFFSET 0x70
+#define GPECON_OFFSET 0x80
+#define GPEDAT_OFFSET 0x84
+#define GPEPUD_OFFSET 0x88
+#define GPECONSLP_OFFSET 0x8C
+#define GPEPUDSLP_OFFSET 0x90
+#define GPFCON_OFFSET 0xA0
+#define GPFDAT_OFFSET 0xA4
+#define GPFPUD_OFFSET 0xA8
+#define GPFCONSLP_OFFSET 0xAC
+#define GPFPUDSLP_OFFSET 0xB0
+#define GPGCON_OFFSET 0xC0
+#define GPGDAT_OFFSET 0xC4
+#define GPGPUD_OFFSET 0xC8
+#define GPGCONSLP_OFFSET 0xCC
+#define GPGPUDSLP_OFFSET 0xD0
+#define GPHCON0_OFFSET 0xE0
+#define GPHCON1_OFFSET 0xE4
+#define GPHDAT_OFFSET 0xE8
+#define GPHPUD_OFFSET 0xEC
+#define GPHCONSLP_OFFSET 0xF0
+#define GPHPUDSLP_OFFSET 0xF4
+#define GPICON_OFFSET 0x100
+#define GPIDAT_OFFSET 0x104
+#define GPIPUD_OFFSET 0x108
+#define GPICONSLP_OFFSET 0x10C
+#define GPIPUDSLP_OFFSET 0x110
+#define GPJCON_OFFSET 0x120
+#define GPJDAT_OFFSET 0x124
+#define GPJPUD_OFFSET 0x128
+#define GPJCONSLP_OFFSET 0x12C
+#define GPJPUDSLP_OFFSET 0x130
+#define MEM0DRVCON_OFFSET 0x1D0
+#define MEM1DRVCON_OFFSET 0x1D4
+#define GPKCON0_OFFSET 0x800
+#define GPKCON1_OFFSET 0x804
+#define GPKDAT_OFFSET 0x808
+#define GPKPUD_OFFSET 0x80C
+#define GPLCON0_OFFSET 0x810
+#define GPLCON1_OFFSET 0x814
+#define GPLDAT_OFFSET 0x818
+#define GPLPUD_OFFSET 0x81C
+#define GPMCON_OFFSET 0x820
+#define GPMDAT_OFFSET 0x824
+#define GPMPUD_OFFSET 0x828
+#define GPNCON_OFFSET 0x830
+#define GPNDAT_OFFSET 0x834
+#define GPNPUD_OFFSET 0x838
+#define GPOCON_OFFSET 0x140
+#define GPODAT_OFFSET 0x144
+#define GPOPUD_OFFSET 0x148
+#define GPOCONSLP_OFFSET 0x14C
+#define GPOPUDSLP_OFFSET 0x150
+#define GPPCON_OFFSET 0x160
+#define GPPDAT_OFFSET 0x164
+#define GPPPUD_OFFSET 0x168
+#define GPPCONSLP_OFFSET 0x16C
+#define GPPPUDSLP_OFFSET 0x170
+#define GPQCON_OFFSET 0x180
+#define GPQDAT_OFFSET 0x184
+#define GPQPUD_OFFSET 0x188
+#define GPQCONSLP_OFFSET 0x18C
+#define GPQPUDSLP_OFFSET 0x190
+
+#define EINTPEND_OFFSET 0x924
+
+#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET)
+#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET)
+#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
+#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
+#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
+#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET)
+#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
+#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
+#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
+#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
+#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET)
+#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
+#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
+#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
+#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
+#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET)
+#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
+#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET)
+#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
+#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
+#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET)
+#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET)
+#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET)
+#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
+#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
+#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET)
+#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET)
+#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET)
+#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
+#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
+#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET)
+#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET)
+#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET)
+#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
+#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
+#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET)
+#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET)
+#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET)
+#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET)
+#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
+#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
+#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET)
+#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET)
+#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET)
+#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
+#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
+#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET)
+#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET)
+#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET)
+#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
+#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
+#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
+#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET)
+#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET)
+#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET)
+#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET)
+#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET)
+#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET)
+#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET)
+#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET)
+#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET)
+#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET)
+#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET)
+#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET)
+#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET)
+#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET)
+#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET)
+#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET)
+#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
+#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
+#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET)
+#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET)
+#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET)
+#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
+#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
+#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET)
+#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET)
+#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET)
+#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
+#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
+
+/*
+ * Bus Matrix
+ */
+#define ELFIN_MEM_SYS_CFG 0x7e00f120
+
+#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
+
+#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
+#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT
+
+#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET)
+#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET)
+#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET)
+#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
+#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
+#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET)
+#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET)
+#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET)
+#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
+#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
+#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET)
+#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET)
+#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET)
+#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
+#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
+#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET)
+#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET)
+#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET)
+#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
+#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
+#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET)
+#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET)
+#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET)
+#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
+#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
+#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET)
+#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET)
+#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET)
+#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
+#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
+#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET)
+#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET)
+#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET)
+#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
+#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
+#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET)
+#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET)
+#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET)
+#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET)
+#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
+#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
+#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET)
+#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET)
+#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET)
+#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
+#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
+#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET)
+#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET)
+#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET)
+#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
+#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
+#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
+#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET)
+#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET)
+#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET)
+#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET)
+#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET)
+#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET)
+#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET)
+#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET)
+#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET)
+#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET)
+#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET)
+#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET)
+#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET)
+#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET)
+#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET)
+#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET)
+#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
+#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
+#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET)
+#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET)
+#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET)
+#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
+#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
+#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET)
+#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET)
+#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET)
+#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
+#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
+
+/*
+ * Memory controller
+ */
+#define ELFIN_SROM_BASE 0x70000000
+
+#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0)
+#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
+#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
+#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
+#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
+#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
+#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
+
+/*
+ * SDRAM Controller
+ */
+#define ELFIN_DMC0_BASE 0x7e000000
+#define ELFIN_DMC1_BASE 0x7e001000
+
+#define INDEX_DMC_MEMC_STATUS 0x00
+#define INDEX_DMC_MEMC_CMD 0x04
+#define INDEX_DMC_DIRECT_CMD 0x08
+#define INDEX_DMC_MEMORY_CFG 0x0C
+#define INDEX_DMC_REFRESH_PRD 0x10
+#define INDEX_DMC_CAS_LATENCY 0x14
+#define INDEX_DMC_T_DQSS 0x18
+#define INDEX_DMC_T_MRD 0x1C
+#define INDEX_DMC_T_RAS 0x20
+#define INDEX_DMC_T_RC 0x24
+#define INDEX_DMC_T_RCD 0x28
+#define INDEX_DMC_T_RFC 0x2C
+#define INDEX_DMC_T_RP 0x30
+#define INDEX_DMC_T_RRD 0x34
+#define INDEX_DMC_T_WR 0x38
+#define INDEX_DMC_T_WTR 0x3C
+#define INDEX_DMC_T_XP 0x40
+#define INDEX_DMC_T_XSR 0x44
+#define INDEX_DMC_T_ESR 0x48
+#define INDEX_DMC_MEMORY_CFG2 0x4C
+#define INDEX_DMC_CHIP_0_CFG 0x200
+#define INDEX_DMC_CHIP_1_CFG 0x204
+#define INDEX_DMC_CHIP_2_CFG 0x208
+#define INDEX_DMC_CHIP_3_CFG 0x20C
+#define INDEX_DMC_USER_STATUS 0x300
+#define INDEX_DMC_USER_CONFIG 0x304
+
+/*
+ * Memory Chip direct command
+ */
+#define DMC_NOP0 0x0c0000
+#define DMC_NOP1 0x1c0000
+#define DMC_PA0 0x000000 /* Precharge all */
+#define DMC_PA1 0x100000
+#define DMC_AR0 0x040000 /* Autorefresh */
+#define DMC_AR1 0x140000
+#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */
+#define DMC_SDR_MR1 0x180032
+#define DMC_DDR_MR0 0x080162
+#define DMC_DDR_MR1 0x180162
+#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */
+#define DMC_mDDR_MR1 0x180032
+#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */
+#define DMC_mSDR_EMR1 0x1a0000
+#define DMC_DDR_EMR0 0x090000
+#define DMC_DDR_EMR1 0x190000
+#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */
+#define DMC_mDDR_EMR1 0x1a0000
+
+/*
+ * Definitions for memory configuration
+ * Set memory configuration
+ * active_chips = 1'b0 (1 chip)
+ * qos_master_chip = 3'b000(ARID[3:0])
+ * memory burst = 3'b010(burst 4)
+ * stop_mem_clock = 1'b0(disable dynamical stop)
+ * auto_power_down = 1'b0(disable auto power-down mode)
+ * power_down_prd = 6'b00_0000(0 cycle for auto power-down)
+ * ap_bit = 1'b0 (bit position of auto-precharge is 10)
+ * row_bits = 3'b010(# row address 13)
+ * column_bits = 3'b010(# column address 10 )
+ *
+ * Set user configuration
+ * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
+ *
+ * Set chip select for chip [n]
+ * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
+ * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
+ */
+
+/*
+ * Nand flash controller
+ */
+#define ELFIN_NAND_BASE 0x70200000
+
+#define NFCONF_OFFSET 0x00
+#define NFCONT_OFFSET 0x04
+#define NFCMMD_OFFSET 0x08
+#define NFADDR_OFFSET 0x0c
+#define NFDATA_OFFSET 0x10
+#define NFMECCDATA0_OFFSET 0x14
+#define NFMECCDATA1_OFFSET 0x18
+#define NFSECCDATA0_OFFSET 0x1c
+#define NFSBLK_OFFSET 0x20
+#define NFEBLK_OFFSET 0x24
+#define NFSTAT_OFFSET 0x28
+#define NFESTAT0_OFFSET 0x2c
+#define NFESTAT1_OFFSET 0x30
+#define NFMECC0_OFFSET 0x34
+#define NFMECC1_OFFSET 0x38
+#define NFSECC_OFFSET 0x3c
+#define NFMLCBITPT_OFFSET 0x40
+
+#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
+#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
+#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
+#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
+#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
+#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
+#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
+#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
+#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
+#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
+#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
+#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
+#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
+#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET)
+#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET)
+#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET)
+#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
+
+#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
+#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
+#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET)
+#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET)
+#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET)
+#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET)
+#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
+#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
+#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
+#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET)
+#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET)
+#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET)
+#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
+#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
+#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET)
+#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
+#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
+#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
+
+#define NFCONF_ECC_4BIT (1<<24)
+
+#define NFCONT_ECC_ENC (1<<18)
+#define NFCONT_WP (1<<16)
+#define NFCONT_MECCLOCK (1<<7)
+#define NFCONT_SECCLOCK (1<<6)
+#define NFCONT_INITMECC (1<<5)
+#define NFCONT_INITSECC (1<<4)
+#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
+#define NFCONT_CS_ALT (1<<2)
+#define NFCONT_CS (1<<1)
+#define NFCONT_ENABLE (1<<0)
+
+#define NFSTAT_ECCENCDONE (1<<7)
+#define NFSTAT_ECCDECDONE (1<<6)
+#define NFSTAT_RnB (1<<0)
+
+#define NFESTAT0_ECCBUSY (1<<31)
+
+/*
+ * Interrupt
+ */
+#define ELFIN_VIC0_BASE_ADDR 0x71200000
+#define ELFIN_VIC1_BASE_ADDR 0x71300000
+#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */
+#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */
+#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */
+#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */
+#define oVECTADDR 0xF00 /* VIC ADDRESS */
+
+/*
+ * Watchdog timer
+ */
+#define ELFIN_WATCHDOG_BASE 0x7E004000
+
+#define WTCON_REG __REG(0x7E004004)
+#define WTDAT_REG __REG(0x7E004008)
+#define WTCNT_REG __REG(0x7E00400C)
+
+
+/*
+ * UART
+ */
+#define ELFIN_UART_BASE 0x7F005000
+
+#define ELFIN_UART0_OFFSET 0x0000
+#define ELFIN_UART1_OFFSET 0x0400
+#define ELFIN_UART2_OFFSET 0x0800
+
+#define ULCON_OFFSET 0x00
+#define UCON_OFFSET 0x04
+#define UFCON_OFFSET 0x08
+#define UMCON_OFFSET 0x0C
+#define UTRSTAT_OFFSET 0x10
+#define UERSTAT_OFFSET 0x14
+#define UFSTAT_OFFSET 0x18
+#define UMSTAT_OFFSET 0x1C
+#define UTXH_OFFSET 0x20
+#define URXH_OFFSET 0x24
+#define UBRDIV_OFFSET 0x28
+#define UDIVSLOT_OFFSET 0x2C
+#define UINTP_OFFSET 0x30
+#define UINTSP_OFFSET 0x34
+#define UINTM_OFFSET 0x38
+
+#define ULCON0_REG __REG(0x7F005000)
+#define UCON0_REG __REG(0x7F005004)
+#define UFCON0_REG __REG(0x7F005008)
+#define UMCON0_REG __REG(0x7F00500C)
+#define UTRSTAT0_REG __REG(0x7F005010)
+#define UERSTAT0_REG __REG(0x7F005014)
+#define UFSTAT0_REG __REG(0x7F005018)
+#define UMSTAT0_REG __REG(0x7F00501c)
+#define UTXH0_REG __REG(0x7F005020)
+#define URXH0_REG __REG(0x7F005024)
+#define UBRDIV0_REG __REG(0x7F005028)
+#define UDIVSLOT0_REG __REG(0x7F00502c)
+#define UINTP0_REG __REG(0x7F005030)
+#define UINTSP0_REG __REG(0x7F005034)
+#define UINTM0_REG __REG(0x7F005038)
+
+#define ULCON1_REG __REG(0x7F005400)
+#define UCON1_REG __REG(0x7F005404)
+#define UFCON1_REG __REG(0x7F005408)
+#define UMCON1_REG __REG(0x7F00540C)
+#define UTRSTAT1_REG __REG(0x7F005410)
+#define UERSTAT1_REG __REG(0x7F005414)
+#define UFSTAT1_REG __REG(0x7F005418)
+#define UMSTAT1_REG __REG(0x7F00541c)
+#define UTXH1_REG __REG(0x7F005420)
+#define URXH1_REG __REG(0x7F005424)
+#define UBRDIV1_REG __REG(0x7F005428)
+#define UDIVSLOT1_REG __REG(0x7F00542c)
+#define UINTP1_REG __REG(0x7F005430)
+#define UINTSP1_REG __REG(0x7F005434)
+#define UINTM1_REG __REG(0x7F005438)
+
+#define UTRSTAT_TX_EMPTY (1 << 2)
+#define UTRSTAT_RX_READY (1 << 0)
+#define UART_ERR_MASK 0xF
+
+/*
+ * PWM timer
+ */
+#define ELFIN_TIMER_BASE 0x7F006000
+
+#define TCFG0_REG __REG(0x7F006000)
+#define TCFG1_REG __REG(0x7F006004)
+#define TCON_REG __REG(0x7F006008)
+#define TCNTB0_REG __REG(0x7F00600c)
+#define TCMPB0_REG __REG(0x7F006010)
+#define TCNTO0_REG __REG(0x7F006014)
+#define TCNTB1_REG __REG(0x7F006018)
+#define TCMPB1_REG __REG(0x7F00601c)
+#define TCNTO1_REG __REG(0x7F006020)
+#define TCNTB2_REG __REG(0x7F006024)
+#define TCMPB2_REG __REG(0x7F006028)
+#define TCNTO2_REG __REG(0x7F00602c)
+#define TCNTB3_REG __REG(0x7F006030)
+#define TCMPB3_REG __REG(0x7F006034)
+#define TCNTO3_REG __REG(0x7F006038)
+#define TCNTB4_REG __REG(0x7F00603c)
+#define TCNTO4_REG __REG(0x7F006040)
+
+/* Fields */
+#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */
+#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */
+#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */
+#define fTCFG1_MUX4 Fld(4, 16)
+/* bits */
+#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
+#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
+#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
+#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
+#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
+#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
+#define COUNT_4_ON (TCON_4_ONOFF * 1)
+#define COUNT_4_OFF (TCON_4_ONOFF * 0)
+#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
+#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1)
+#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
+#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
+#define TIMER3_IVT_ON (TCON_3_INVERT * 1)
+#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
+#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
+#define TIMER3_MANUP (TCON_3_MAN*1)
+#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
+#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
+#define TIMER3_ON (TCON_3_ONOFF * 1)
+#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
+
+#if defined(CONFIG_CLK_400_100_50)
+#define STARTUP_AMDIV 400
+#define STARTUP_MDIV 400
+#define STARTUP_PDIV 6
+#define STARTUP_SDIV 1
+#elif defined(CONFIG_CLK_400_133_66)
+#define STARTUP_AMDIV 400
+#define STARTUP_MDIV 533
+#define STARTUP_PDIV 6
+#define STARTUP_SDIV 1
+#elif defined(CONFIG_CLK_533_133_66)
+#define STARTUP_AMDIV 533
+#define STARTUP_MDIV 533
+#define STARTUP_PDIV 6
+#define STARTUP_SDIV 1
+#elif defined(CONFIG_CLK_667_133_66)
+#define STARTUP_AMDIV 667
+#define STARTUP_MDIV 533
+#define STARTUP_PDIV 6
+#define STARTUP_SDIV 1
+#endif
+
+#define STARTUP_PCLKDIV 3
+#define STARTUP_HCLKX2DIV 1
+#define STARTUP_HCLKDIV 1
+#define STARTUP_MPLLDIV 1
+#define STARTUP_APLLDIV 0
+
+#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
+ (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
+#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
+ (STARTUP_PDIV << 8) | STARTUP_SDIV)
+#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
+ STARTUP_PDIV) * STARTUP_MDIV)
+
+#if defined(CONFIG_SYNC_MODE)
+#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
+ (STARTUP_PDIV << 8) | STARTUP_SDIV)
+#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
+ STARTUP_PDIV) * STARTUP_MDIV)
+#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
+ (STARTUP_HCLKDIV + 1))
+#else
+#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
+ (STARTUP_PDIV << 8) | STARTUP_SDIV)
+#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
+ STARTUP_PDIV) * STARTUP_AMDIV)
+#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
+ (STARTUP_HCLKDIV + 1))
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
+#define DMC1_MEM_CFG2 0xB45
+#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
+#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
+
+/* Memory Parameters */
+/* DDR Parameters */
+#define DDR_tREFRESH 7800 /* ns */
+#define DDR_tRAS 45 /* ns (min: 45ns)*/
+#define DDR_tRC 68 /* ns (min: 67.5ns)*/
+#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
+#define DDR_tRFC 80 /* ns (min: 80ns)*/
+#define DDR_tRP 23 /* ns (min: 22.5ns)*/
+#define DDR_tRRD 15 /* ns (min: 15ns)*/
+#define DDR_tWR 15 /* ns (min: 15ns)*/
+#define DDR_tXSR 120 /* ns (min: 120ns)*/
+#define DDR_CASL 3 /* CAS Latency 3 */
+
+/*
+ * mDDR memory configuration
+ */
+
+#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
+
+#define DMC_DDR_BA_EMRS 2
+#define DMC_DDR_MEM_CASLAT 3
+/* 6 Set Cas Latency to 3 */
+#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1)
+/* Min 0.75 ~ 1.25 */
+#define DMC_DDR_t_DQSS 1
+/* Min 2 tck */
+#define DMC_DDR_t_MRD 2
+/* 7, Min 45ns */
+#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1)
+/* 10, Min 67.5ns */
+#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1)
+/* 4,5(TRM), Min 22.5ns */
+#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1)
+#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
+/* 11,18(TRM) Min 80ns */
+#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1)
+#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
+/* 4, 5(TRM) Min 22.5ns */
+#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1)
+#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
+/* 3, Min 15ns */
+#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1)
+/* Min 15ns */
+#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1)
+#define DMC_DDR_t_WTR 2
+/* 1tck + tIS(1.5ns) */
+#define DMC_DDR_t_XP 2
+/* 17, Min 120ns */
+#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1)
+#define DMC_DDR_t_ESR DMC_DDR_t_XSR
+/* TRM 2656 */
+#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH))
+/* 2b01 : mDDR */
+#define DMC_DDR_USER_CONFIG 1
+
+#ifndef __ASSEMBLY__
+enum s3c64xx_uarts_nr {
+ S3C64XX_UART0,
+ S3C64XX_UART1,
+ S3C64XX_UART2,
+};
+
+#include "s5pc100.h"
+
+static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
+{
+ return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
+}
+#endif
+
+#endif /*__S3C6400_H__*/
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
- misc_init_r ();
+ /* inki */
+ //misc_init_r ();
#endif
/* enable exceptions */
projects / kernel / u-boot.git / commitdiff