* mips-opc.c: Change div machine instruction to be z,s,t rather

	than s,t.  Change div macro to be d,v,t rather than d,s,t.
	Likewise for divu, ddiv, ddivu.  Added z,s,t case for drem, dremu,
	rem and remu which generates only the corresponding div
	instruction.  This is for compatibility with the MIPS assembler,
	which only generates the simple machine instruction when an
	explicit destination of $0 is used.
	* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 16cad1c..4e8676a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,10 +1,13 @@
 Thu Sep  2 10:35:25 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
 
-       * mips-opc.c: Move div machine instruction after macro forms.
-       Change d,s,t form to d,v,t.  Likewise for divu, ddiv and ddivu.
-       This is for compatibility with the MIPS assembler, which only
-       generates the simple machine instruction when an explicit
-       destination of $0 is used.
+       * mips-opc.c: Change div machine instruction to be z,s,t rather
+       than s,t.  Change div macro to be d,v,t rather than d,s,t.
+       Likewise for divu, ddiv, ddivu.  Added z,s,t case for drem, dremu,
+       rem and remu which generates only the corresponding div
+       instruction.  This is for compatibility with the MIPS assembler,
+       which only generates the simple machine instruction when an
+       explicit destination of $0 is used.
+       * mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
 
 Thu Aug 26 17:41:44 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
 

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 6806bcd..6ccd8c7 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -49,7 +49,7 @@ static CONST char * CONST reg_names[] = REGISTER_NAMES;
 /* subroutine */
 static void
 print_insn_arg (d, l, pc, info)
-     char *d;
+     const char *d;
      register unsigned long int l;
      bfd_vma pc;
      struct disassemble_info *info;
@@ -114,6 +114,10 @@ print_insn_arg (d, l, pc, info)
                             reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
       break;
 
+    case 'z':
+      (*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
+      break;
+
     case '<':
       (*info->fprintf_func) (info->stream, "0x%x",
                             (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
@@ -180,7 +184,7 @@ _print_insn_mips (memaddr, word, info)
      unsigned long int word;
 {
   register int i;
-  register char *d;
+  register const char *d;
 
   for (i = 0; i < NUMOPCODES; i++)
     {

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index abd9f61..d1e3e14 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -240,28 +240,26 @@ const struct mips_opcode mips_opcodes[] = {
 {"daddu",   "d,v,t",   0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
 {"daddu",   "t,r,I",   3,    (int) M_DADDU_I,  INSN_MACRO      },
 /* For ddiv, see the comments about div.  */
+{"ddiv",    "z,s,t",   0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 {"ddiv",    "d,v,t",   3,    (int) M_DDIV_3,   INSN_MACRO      },
 {"ddiv",    "d,v,I",   3,    (int) M_DDIV_3I,  INSN_MACRO      },
-{"ddiv",    "s,t",     0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 /* For ddivu, see the comments about div.  */
+{"ddivu",   "z,s,t",   0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 {"ddivu",   "d,v,t",   3,    (int) M_DDIVU_3,  INSN_MACRO      },
 {"ddivu",   "d,v,I",   3,    (int) M_DDIVU_3I, INSN_MACRO      },
-{"ddivu",   "s,t",     0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 /* The MIPS assembler treats the div opcode with two operands as
    though the first operand appeared twice (the first operand is both
    a source and a destination).  To get the div machine instruction,
-   you must use an explicit destination of $0.  The final case of
-   "div" is the machine instruction itself, but actually a user
-   instruction will never match it (it will match d,v,t first).  */
+   you must use an explicit destination of $0.  */
+{"div",     "z,s,t",   0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 {"div",     "d,v,t",   0,    (int) M_DIV_3,    INSN_MACRO      },
 {"div",     "d,v,I",   0,    (int) M_DIV_3I,   INSN_MACRO      },
-{"div",     "s,t",     0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 {"div.d",   "D,V,T",   0x46200003, 0xffe0003f, WR_D|RD_S|RD_T  },
 {"div.s",   "D,V,T",   0x46000003, 0xffe0003f, WR_D|RD_S|RD_T  },
 /* For divu, see the comments about div.  */
+{"divu",    "z,s,t",   0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 {"divu",    "d,v,t",   0,    (int) M_DIVU_3,   INSN_MACRO      },
 {"divu",    "d,v,I",   0,    (int) M_DIVU_3I,  INSN_MACRO      },
-{"divu",    "s,t",     0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 {"dmfc0",   "t,G",     0x40200000, 0xffe007ff, LCD|WR_t|RD_C0|I3 },
 {"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC|I3 },
 {"dmfc1",   "t,S",     0x44200000, 0xffe007ff, LCD|WR_t|RD_S|I3 },
@@ -276,8 +274,10 @@ const struct mips_opcode mips_opcodes[] = {
 {"dmultu",  "s,t",     0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 {"dneg",    "d,w",     0x0000002e, 0xffe007ff, WR_d|RD_t|I3    }, /* dsub 0 */
 {"dnegu",   "d,w",     0x0000002f, 0xffe007ff, WR_d|RD_t|I3    }, /* dsubu 0*/
+{"drem",    "z,s,t",   0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 {"drem",    "d,v,t",   3,    (int) M_DREM_3,   INSN_MACRO      },
 {"drem",    "d,v,I",   3,    (int) M_DREM_3I,  INSN_MACRO      },
+{"dremu",   "z,s,t",   0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 {"dremu",   "d,v,t",   3,    (int) M_DREMU_3,  INSN_MACRO      },
 {"dremu",   "d,v,I",   3,    (int) M_DREMU_3I, INSN_MACRO      },
 {"dsllv",   "d,t,s",   0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
@@ -409,8 +409,10 @@ const struct mips_opcode mips_opcodes[] = {
 {"or",      "d,v,t",   0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t  },
 {"or",      "t,r,I",   0,    (int) M_OR_I,     INSN_MACRO      },
 {"ori",     "t,r,i",   0x34000000, 0xfc000000, WR_t|RD_s       },
+{"rem",     "z,s,t",   0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
 {"rem",     "d,v,t",   0,    (int) M_REM_3,    INSN_MACRO      },
 {"rem",     "d,v,I",   0,    (int) M_REM_3I,   INSN_MACRO      },
+{"remu",    "z,s,t",   0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
 {"remu",    "d,v,t",   0,    (int) M_REMU_3,   INSN_MACRO      },
 {"remu",    "d,v,I",   0,    (int) M_REMU_3I,  INSN_MACRO      },
 {"rfe",     "",                0x42000010, 0xffffffff, INSN_RFE        },