drm/amdgpu: add a callback to set vm mapping flags

This lets each asic set whichever flags it supports.

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index abf2b39..00553bf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -296,6 +296,9 @@ struct amdgpu_gart_funcs {
                           uint64_t flags); /* access flags */
        /* enable/disable PRT support */
        void (*set_prt)(struct amdgpu_device *adev, bool enable);
+       /* set pte flags based per asic */
+       uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
+                                    uint32_t flags);
 };
 
 /* provided by the ih block */
@@ -1682,6 +1685,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
+#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 3c22656..6daf004 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -569,7 +569,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
        struct ttm_validate_buffer tv;
        struct ww_acquire_ctx ticket;
        struct list_head list;
-       uint64_t va_flags = 0;
+       uint64_t va_flags;
        int r = 0;
 
        if (!adev->vm_manager.enabled)
@@ -631,14 +631,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 
        switch (args->operation) {
        case AMDGPU_VA_OP_MAP:
-               if (args->flags & AMDGPU_VM_PAGE_READABLE)
-                       va_flags |= AMDGPU_PTE_READABLE;
-               if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
-                       va_flags |= AMDGPU_PTE_WRITEABLE;
-               if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
-                       va_flags |= AMDGPU_PTE_EXECUTABLE;
-               if (args->flags & AMDGPU_VM_PAGE_PRT)
-                       va_flags |= AMDGPU_PTE_PRT;
+               va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
+
                r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
                                     args->offset_in_bo, args->map_size,
                                     va_flags);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 6a1f566..35f74c6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -379,6 +379,21 @@ static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
        return 0;
 }
 
+static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
+                                         uint32_t flags)
+{
+       uint64_t pte_flag = 0;
+
+       if (flags & AMDGPU_VM_PAGE_READABLE)
+               pte_flag |= AMDGPU_PTE_READABLE;
+       if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+               pte_flag |= AMDGPU_PTE_WRITEABLE;
+       if (flags & AMDGPU_VM_PAGE_PRT)
+               pte_flag |= AMDGPU_PTE_PRT;
+
+       return pte_flag;
+}
+
 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
                                              bool value)
 {
@@ -1138,6 +1153,7 @@ static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
        .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
        .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
        .set_prt = gmc_v6_0_set_prt,
+       .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 9f41d9f..dc9b6d6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -451,6 +451,21 @@ static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
        return 0;
 }
 
+static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
+                                         uint32_t flags)
+{
+       uint64_t pte_flag = 0;
+
+       if (flags & AMDGPU_VM_PAGE_READABLE)
+               pte_flag |= AMDGPU_PTE_READABLE;
+       if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+               pte_flag |= AMDGPU_PTE_WRITEABLE;
+       if (flags & AMDGPU_VM_PAGE_PRT)
+               pte_flag |= AMDGPU_PTE_PRT;
+
+       return pte_flag;
+}
+
 /**
  * gmc_v8_0_set_fault_enable_default - update VM fault handling
  *
@@ -1323,6 +1338,7 @@ static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
        .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
        .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
        .set_prt = gmc_v7_0_set_prt,
+       .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 233ac35..c087b00 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -563,6 +563,23 @@ static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
        return 0;
 }
 
+static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
+                                         uint32_t flags)
+{
+       uint64_t pte_flag = 0;
+
+       if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
+               pte_flag |= AMDGPU_PTE_EXECUTABLE;
+       if (flags & AMDGPU_VM_PAGE_READABLE)
+               pte_flag |= AMDGPU_PTE_READABLE;
+       if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+               pte_flag |= AMDGPU_PTE_WRITEABLE;
+       if (flags & AMDGPU_VM_PAGE_PRT)
+               pte_flag |= AMDGPU_PTE_PRT;
+
+       return pte_flag;
+}
+
 /**
  * gmc_v8_0_set_fault_enable_default - update VM fault handling
  *
@@ -1562,6 +1579,7 @@ static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
        .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
        .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
        .set_prt = gmc_v8_0_set_prt,
+       .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {