drm/v3d: Don't clear MMU control bits on exception

MMU exception conditions are reported in the V3D_MMU_CTRL register as
write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any
exceptions, but does so by masking out any other bits and writing the
result back. There are some important control bits in that register,
including MMU_ENABLE, so a safer approach is to simply write back the
value just read unaltered.

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/1608755714-18233-4-git-send-email-stefan.wahren@i2se.com

diff --git a/drivers/gpu/drm/v3d/v3d_irq.c b/drivers/gpu/drm/v3d/v3d_irq.c
index 0be2eb7876bed20ef78b304602fefa7bb5649141..e714d5318f3095c2f3d23692d23da98f7247389f 100644 (file)
--- a/drivers/gpu/drm/v3d/v3d_irq.c
+++ b/drivers/gpu/drm/v3d/v3d_irq.c
@@ -178,10 +178,7 @@ v3d_hub_irq(int irq, void *arg)
                };
                const char *client = "?";
 
-               V3D_WRITE(V3D_MMU_CTL,
-                         V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |
-                                                  V3D_MMU_CTL_PT_INVALID |
-                                                  V3D_MMU_CTL_WRITE_VIOLATION));
+               V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
 
                if (v3d->ver >= 41) {
                        axi_id = axi_id >> 5;