rockchip: move ROCKCHIP_STIMER_BASE to Kconfig
authorJohan Jonker <jbx6244@gmail.com>
Sat, 9 Apr 2022 16:55:02 +0000 (18:55 +0200)
committerKever Yang <kever.yang@rock-chips.com>
Mon, 18 Apr 2022 03:25:12 +0000 (11:25 +0800)
Move ROCKCHIP_STIMER_BASE to Kconfig.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
22 files changed:
arch/arm/mach-rockchip/Kconfig
arch/arm/mach-rockchip/px30/Kconfig
arch/arm/mach-rockchip/rk3036/Kconfig
arch/arm/mach-rockchip/rk3128/Kconfig
arch/arm/mach-rockchip/rk322x/Kconfig
arch/arm/mach-rockchip/rk3288/Kconfig
arch/arm/mach-rockchip/rk3308/Kconfig
arch/arm/mach-rockchip/rk3328/Kconfig
arch/arm/mach-rockchip/rk3368/Kconfig
arch/arm/mach-rockchip/rk3399/Kconfig
arch/arm/mach-rockchip/rk3568/Kconfig
configs/rock_defconfig
include/configs/px30_common.h
include/configs/rk3036_common.h
include/configs/rk3128_common.h
include/configs/rk322x_common.h
include/configs/rk3288_common.h
include/configs/rk3308_common.h
include/configs/rk3328_common.h
include/configs/rk3368_common.h
include/configs/rk3399_common.h
include/configs/rk3568_common.h

index 308dc09..8119649 100644 (file)
@@ -339,6 +339,16 @@ config ROCKCHIP_BOOT_MODE_REG
          The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
          according to the value from this register.
 
+config ROCKCHIP_STIMER
+       bool "Rockchip STIMER support"
+       default y
+       help
+         Enable Rockchip STIMER support.
+
+config ROCKCHIP_STIMER_BASE
+       hex
+       depends on ROCKCHIP_STIMER
+
 config ROCKCHIP_SPL_RESERVE_IRAM
        hex "Size of IRAM reserved in SPL"
        default 0
index 145bf35..4886fe9 100644 (file)
@@ -38,6 +38,9 @@ config TARGET_PX30_CORE
 config ROCKCHIP_BOOT_MODE_REG
        default 0xff010200
 
+config ROCKCHIP_STIMER_BASE
+       default 0xff220020
+
 config SYS_SOC
        default "px30"
 
index b746795..111531b 100644 (file)
@@ -16,6 +16,9 @@ endchoice
 config ROCKCHIP_BOOT_MODE_REG
        default 0x200081c8
 
+config ROCKCHIP_STIMER_BASE
+       default 0x200440a0
+
 config SYS_SOC
        default "rk3036"
 
index b867401..9cc494e 100644 (file)
@@ -16,6 +16,9 @@ endchoice
 config ROCKCHIP_BOOT_MODE_REG
        default 0x100a0038
 
+config ROCKCHIP_STIMER_BASE
+       default 0x200440a0
+
 config SYS_SOC
        default "rk3128"
 
index 6458cd5..058f848 100644 (file)
@@ -8,6 +8,9 @@ config TARGET_EVB_RK3229
 config ROCKCHIP_BOOT_MODE_REG
        default 0x110005c8
 
+config ROCKCHIP_STIMER_BASE
+       default 0x110d0020
+
 config SYS_SOC
        default "rk322x"
 
index f37b1bd..dd8c782 100644 (file)
@@ -148,6 +148,9 @@ config ROCKCHIP_FAST_SPL
 config ROCKCHIP_BOOT_MODE_REG
        default 0xff730094
 
+config ROCKCHIP_STIMER_BASE
+       default 0xff810020
+
 config SYS_SOC
        default "rk3288"
 
index 8fa536e..194353e 100644 (file)
@@ -8,6 +8,12 @@ config TARGET_ROC_RK3308_CC
        bool "Firefly roc-rk3308-cc"
        select BOARD_LATE_INIT
 
+config ROCKCHIP_BOOT_MODE_REG
+       default 0xff000500
+
+config ROCKCHIP_STIMER_BASE
+       default 0xff1b00a0
+
 config SYS_SOC
        default "rk3308"
 
@@ -17,10 +23,6 @@ config SYS_MALLOC_F_LEN
 config SPL_SERIAL
        default y
 
-config ROCKCHIP_BOOT_MODE_REG
-       default 0xff000500
-
-
 source "board/rockchip/evb_rk3308/Kconfig"
 source "board/firefly/firefly-rk3308/Kconfig"
 
index d13a169..f6f1e06 100644 (file)
@@ -15,6 +15,9 @@ endchoice
 config ROCKCHIP_BOOT_MODE_REG
        default 0xff1005c8
 
+config ROCKCHIP_STIMER_BASE
+       default 0xff1d0020
+
 config SYS_SOC
        default "rk3328"
 
index 78eb96d..104db36 100644 (file)
@@ -45,6 +45,9 @@ endchoice
 config ROCKCHIP_BOOT_MODE_REG
        default 0xff738200
 
+config ROCKCHIP_STIMER_BASE
+       default 0xff830020
+
 config SYS_SOC
        default "rk3368"
 
index 0833e08..c1f2513 100644 (file)
@@ -125,6 +125,9 @@ endchoice
 config ROCKCHIP_BOOT_MODE_REG
        default 0xff320300
 
+config ROCKCHIP_STIMER_BASE
+       default 0xff8680a0
+
 config SYS_SOC
        default "rk3399"
 
index 201c63c..4e7c02c 100644 (file)
@@ -9,6 +9,9 @@ config TARGET_EVB_RK3568
 config ROCKCHIP_BOOT_MODE_REG
        default 0xfdc20200
 
+config ROCKCHIP_STIMER_BASE
+       default 0xfdd1c020
+
 config SYS_SOC
        default "rk3568"
 
index 290f5af..4aa4608 100644 (file)
@@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
 CONFIG_SPL_TEXT_BASE=0x10080800
 CONFIG_ROCKCHIP_RK3188=y
+# CONFIG_ROCKCHIP_STIMER is not set
 CONFIG_TARGET_ROCK=y
 CONFIG_SPL_STACK_R_ADDR=0x60080000
 CONFIG_DEBUG_UART_BASE=0x20064000
index 0992387..dc60901 100644 (file)
@@ -12,7 +12,6 @@
 
 #define CONFIG_SYS_NS16550_MEM32
 
-#define CONFIG_ROCKCHIP_STIMER_BASE    0xff220020
 #define COUNTER_FREQUENCY              24000000
 
 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
index 00c453d..5905518 100644 (file)
@@ -10,7 +10,6 @@
 
 #define CONFIG_SYS_CBSIZE              1024
 
-#define CONFIG_ROCKCHIP_STIMER_BASE    0x200440a0
 #define COUNTER_FREQUENCY              24000000
 #define CONFIG_SYS_HZ_CLOCK            24000000
 
index 97cacea..d77a7d7 100644 (file)
@@ -11,7 +11,6 @@
 #define CONFIG_SYS_MAXARGS             16
 #define CONFIG_SYS_CBSIZE              1024
 
-#define CONFIG_ROCKCHIP_STIMER_BASE    0x200440a0
 #define COUNTER_FREQUENCY              24000000
 #define CONFIG_SYS_HZ_CLOCK            24000000
 
index ef55ef0..3258820 100644 (file)
@@ -11,7 +11,6 @@
 #define CONFIG_SYS_CBSIZE              1024
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /*  64M */
 
-#define CONFIG_ROCKCHIP_STIMER_BASE    0x110d0020
 #define COUNTER_FREQUENCY              24000000
 #define CONFIG_SYS_HZ_CLOCK            24000000
 
index 490da7c..e2e0f70 100644 (file)
@@ -13,7 +13,6 @@
 
 #define CONFIG_SYS_CBSIZE              1024
 
-#define CONFIG_ROCKCHIP_STIMER_BASE    0xff810020
 #define COUNTER_FREQUENCY              24000000
 #define CONFIG_SYS_HZ_CLOCK            24000000
 
index 1664707..9cda8d9 100644 (file)
@@ -15,7 +15,6 @@
 
 #define CONFIG_SYS_NS16550_MEM32
 
-#define CONFIG_ROCKCHIP_STIMER_BASE    0xff1b00a0
 #define CONFIG_IRAM_BASE               0xfff80000
 #define CONFIG_SYS_INIT_SP_ADDR                0x00800000
 #define CONFIG_SPL_STACK               0x00400000
index c1e26a0..8a5f0c8 100644 (file)
@@ -10,7 +10,6 @@
 
 #define CONFIG_IRAM_BASE               0xff090000
 
-#define CONFIG_ROCKCHIP_STIMER_BASE    0xff1d0020
 #define COUNTER_FREQUENCY              24000000
 
 #define CONFIG_SYS_CBSIZE              1024
index 8b239ca..239296c 100644 (file)
@@ -15,7 +15,6 @@
 #define SDRAM_MAX_SIZE                 0xff000000
 #define CONFIG_SYS_CBSIZE              1024
 
-#define CONFIG_ROCKCHIP_STIMER_BASE    0xff830020
 #define COUNTER_FREQUENCY              24000000
 
 #define CONFIG_IRAM_BASE               0xff8c0000
index ed72c8b..4037dba 100644 (file)
@@ -11,7 +11,6 @@
 #define CONFIG_SYS_CBSIZE              1024
 
 #define COUNTER_FREQUENCY               24000000
-#define CONFIG_ROCKCHIP_STIMER_BASE    0xff8680a0
 
 #define CONFIG_IRAM_BASE               0xff8c0000
 
index 25d7c5c..5649cd6 100644 (file)
@@ -11,7 +11,6 @@
 #define CONFIG_SYS_CBSIZE              1024
 
 #define COUNTER_FREQUENCY               24000000
-#define CONFIG_ROCKCHIP_STIMER_BASE    0xfdd1c020
 
 #define CONFIG_IRAM_BASE               0xfdcc0000