drm/amdgpu/soc15: add support for navy_flounder

Add soc support.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a2ab80e..665fb4c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -754,6 +754,12 @@ static int nv_common_early_init(void *handle)
                }
                adev->external_rev_id = adev->rev_id + 0x28;
                break;
+       case CHIP_NAVY_FLOUNDER:
+               adev->cg_flags = 0;
+               adev->pg_flags = 0;
+               adev->external_rev_id = adev->rev_id + 0x32;
+               break;
+
        default:
                /* FIXME: not supported yet */
                return -EINVAL;
@@ -980,6 +986,7 @@ static int nv_common_set_clockgating_state(void *handle,
        case CHIP_NAVI14:
        case CHIP_NAVI12:
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                adev->nbio.funcs->update_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE);
                adev->nbio.funcs->update_medium_grain_light_sleep(adev,