#include <time.h>
#include "errno.h"
-#include "common/intel_clflush.h"
+#include "common/intel_mem.h"
#include "dev/intel_debug.h"
#include "common/intel_gem.h"
#include "dev/intel_device_info.h"
#include "errno.h"
#include "common/intel_aux_map.h"
-#include "common/intel_clflush.h"
+#include "common/intel_mem.h"
#include "dev/intel_debug.h"
#include "common/intel_gem.h"
#include "dev/intel_device_info.h"
* IN THE SOFTWARE.
*/
-#ifndef INTEL_CLFLUSH_H
-#define INTEL_CLFLUSH_H
+#include "intel_mem.h"
-#define CACHELINE_SIZE 64
-#define CACHELINE_MASK 63
+#include <stdint.h>
#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
-static inline void
+void
intel_clflush_range(void *start, size_t size)
{
void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
}
}
-static inline void
+void
intel_flush_range(void *start, size_t size)
{
__builtin_ia32_mfence();
intel_clflush_range(start, size);
}
-static inline void
+void
intel_invalidate_range(void *start, size_t size)
{
if (size == 0)
__builtin_ia32_mfence();
}
#endif /* SUPPORT_INTEL_INTEGRATED_GPUS */
-
-#endif
--- /dev/null
+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef INTEL_MEM_H
+#define INTEL_MEM_H
+
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CACHELINE_SIZE 64
+#define CACHELINE_MASK 63
+
+#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
+void intel_clflush_range(void *start, size_t size);
+void intel_flush_range(void *start, size_t size);
+void intel_invalidate_range(void *start, size_t size);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* INTEL_MEM_H */
'intel_aux_map.c',
'intel_aux_map.h',
'intel_buffer_alloc.h',
- 'intel_clflush.h',
'intel_decoder.h',
'intel_disasm.c',
'intel_disasm.h',
'intel_uuid.h',
'intel_measure.c',
'intel_measure.h',
+ 'intel_mem.c',
+ 'intel_mem.h',
'intel_pixel_hash.h'
)
#define MESA_LOG_TAG "INTEL-SANITIZE-GPU"
#include "util/log.h"
-#include "common/intel_clflush.h"
+#include "common/intel_mem.h"
static int (*libc_open)(const char *pathname, int flags, mode_t mode);
static int (*libc_close)(int fd);
#define VG(x) ((void)0)
#endif
-#include "common/intel_clflush.h"
#include "common/intel_decoder.h"
#include "common/intel_engine.h"
#include "common/intel_gem.h"
#include "common/intel_l3_config.h"
#include "common/intel_measure.h"
+#include "common/intel_mem.h"
#include "common/intel_sample_positions.h"
#include "dev/intel_device_info.h"
#include "blorp/blorp.h"
#define VG(x) ((void)0)
#endif
-#include "common/intel_clflush.h"
#include "common/intel_decoder.h"
#include "common/intel_engine.h"
#include "common/intel_gem.h"
#include "common/intel_l3_config.h"
#include "common/intel_measure.h"
+#include "common/intel_mem.h"
#include "common/intel_sample_positions.h"
#include "dev/intel_device_info.h"
#include "blorp/blorp.h"