ARM: shmobile: r8a7791 dtsi: Add MSIOF nodes and aliases
authorGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Tue, 25 Feb 2014 10:30:16 +0000 (11:30 +0100)
committerStephane Desneux <stephane.desneux@open.eurogiciel.org>
Wed, 4 Feb 2015 10:14:57 +0000 (11:14 +0100)
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 7713d3abe220c7d578768c07d183f6efbfa8895b)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7791.dtsi

index 46aa2f1..082644c 100644 (file)
@@ -28,6 +28,9 @@
                i2c4 = &i2c4;
                i2c5 = &i2c5;
                spi0 = &qspi;
+               spi1 = &msiof0;
+               spi2 = &msiof1;
+               spi3 = &msiof2;
        };
 
        cpus {
                #size-cells = <0>;
                status = "disabled";
        };
+
+       msiof0: spi@e6e20000 {
+               compatible = "renesas,msiof-r8a7791";
+               reg = <0 0xe6e20000 0 0x0064>;
+               interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       msiof1: spi@e6e10000 {
+               compatible = "renesas,msiof-r8a7791";
+               reg = <0 0xe6e10000 0 0x0064>;
+               interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       msiof2: spi@e6e00000 {
+               compatible = "renesas,msiof-r8a7791";
+               reg = <0 0xe6e00000 0 0x0064>;
+               interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
 };