drm/amdgpu: introduce two work mode for imu

IMU has two work mode such as debug mode and mission mode. Current GC
v11_0_0 is using the debug mode.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
index 56cf127..cfc4a92 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
@@ -24,6 +24,11 @@
 #ifndef __AMDGPU_IMU_H__
 #define __AMDGPU_IMU_H__
 
+enum imu_work_mode {
+       DEBUG_MODE,
+       MISSION_MODE
+};
+
 struct amdgpu_imu_funcs {
     int (*init_microcode)(struct amdgpu_device *adev);
     int (*load_microcode)(struct amdgpu_device *adev);
@@ -46,6 +51,7 @@ struct imu_rlc_ram_golden {
 
 struct amdgpu_imu {
     const struct amdgpu_imu_funcs *funcs;
+    enum imu_work_mode mode;
 };
 
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 10e180b..abe2274 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6292,6 +6292,7 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
 
 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
 {
+       adev->gfx.imu.mode = DEBUG_MODE;
        adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index d63d3f2..05d2b93 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -125,9 +125,11 @@ static void imu_v11_0_setup(struct amdgpu_device *adev)
        WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
        WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);
 
-       imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
-       imu_reg_val |= 0x1;
-       WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+       if (adev->gfx.imu.mode == DEBUG_MODE) {
+               imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
+               imu_reg_val |= 0x1;
+               WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+       }
 
        //disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB
        imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);
@@ -144,16 +146,18 @@ static int imu_v11_0_start(struct amdgpu_device *adev)
        imu_reg_val &= 0xfffffffe;
        WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
 
-       for (i = 0; i < adev->usec_timeout; i++) {
-               imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
-               if ((imu_reg_val & 0x1f) == 0x1f)
-                       break;
-               udelay(1);
-       }
-
-       if (i >= adev->usec_timeout) {
-               dev_err(adev->dev, "init imu: IMU start timeout\n");
-               return -ETIMEDOUT;
+       if (adev->gfx.imu.mode == DEBUG_MODE) {
+               for (i = 0; i < adev->usec_timeout; i++) {
+                       imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
+                       if ((imu_reg_val & 0x1f) == 0x1f)
+                               break;
+                       udelay(1);
+               }
+
+               if (i >= adev->usec_timeout) {
+                       dev_err(adev->dev, "init imu: IMU start timeout\n");
+                       return -ETIMEDOUT;
+               }
        }
 
        return 0;