dt-binding: memory: pl353-smc: Fix the example syntax and style

Enhance the spacing, the comment style, add { }, remove (...).

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210610082040.2075611-6-miquel.raynal@bootlin.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
index 105160c..46e17f5 100644 (file)
--- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
@@ -24,27 +24,29 @@ Required device node properties:
                        of the memory region requested by the device.
 
 Example:
-       smcc: memory-controller@e000e000
-                       compatible = "arm,pl353-smc-r2p1", "arm,primecell";
-                       clock-names = "memclk", "apb_pclk";
-                       clocks = <&clkc 11>, <&clkc 44>;
-                       reg = <0xe000e000 0x1000>;
-                       #address-cells = <2>;
-                       #size-cells = <1>;
-                       ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
-                                 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
-                                 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
-                       nand_0: flash@e1000000 {
-                               compatible = "arm,pl353-nand-r2p1"
-                               reg = <0 0 0x1000000>;
-                               (...)
-                       };
-                       nor0: flash@e2000000 {
-                               compatible = "cfi-flash";
-                               reg = <1 0 0x2000000>;
-                       };
-                       nor1: flash@e4000000 {
-                               compatible = "cfi-flash";
-                               reg = <2 0 0x2000000>;
-                       };
+       smcc: memory-controller@e000e000 {
+               compatible = "arm,pl353-smc-r2p1", "arm,primecell";
+               clock-names = "memclk", "apb_pclk";
+               clocks = <&clkc 11>, <&clkc 44>;
+               reg = <0xe000e000 0x1000>;
+               #address-cells = <2>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
+                         0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
+                         0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
+
+               nand_0: flash@e1000000 {
+                       compatible = "arm,pl353-nand-r2p1";
+                       reg = <0 0 0x1000000>;
+               };
+
+               nor0: flash@e2000000 {
+                       compatible = "cfi-flash";
+                       reg = <1 0 0x2000000>;
+               };
+
+               nor1: flash@e4000000 {
+                       compatible = "cfi-flash";
+                       reg = <2 0 0x2000000>;
+               };
        };