s5pc100: universal: Use r0 for clock base

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

diff --git a/board/samsung/universal/lowlevel_init.S b/board/samsung/universal/lowlevel_init.S
index a146439..6689538 100644 (file)
--- a/board/samsung/universal/lowlevel_init.S
+++ b/board/samsung/universal/lowlevel_init.S
@@ -190,18 +190,18 @@ wakeup_reset:
  * void system_clock_init(void)
  */
 system_clock_init:
-       ldr     r6, =S5P_PA_CLK                 @ 0xE0100000
+       ldr     r0, =S5PC1XX_CLOCK_BASE         @ 0xE0100000
 
        /* Check S5PC100 */
        cmp     r7, r8
        bne     110f
-
+100:
        /* Set Lock Time */
        ldr     r1, =0xe10                      @ Locktime : 0xe10 = 3600
-       str     r1, [r6, #0x000]                @ S5P_APLL_LOCK
-       str     r1, [r6, #0x004]                @ S5P_MPLL_LOCK
-       str     r1, [r6, #0x008]                @ S5P_EPLL_LOCK
-       str     r1, [r6, #0x00C]                @ S5P_HPLL_LOCK
+       str     r1, [r0, #0x000]                @ S5PC100_APLL_LOCK
+       str     r1, [r0, #0x004]                @ S5PC100_MPLL_LOCK
+       str     r1, [r0, #0x008]                @ S5PC100_EPLL_LOCK
+       str     r1, [r0, #0x00C]                @ S5PC100_HPLL_LOCK
 
        /* S5P_APLL_CON */
 #ifdef CONFIG_CLK_667_166_83
@@ -221,24 +221,24 @@ system_clock_init:
 #else
 #error you should set the correct clock configuration
 #endif
-       str     r1, [r6, #0x100]
+       str     r1, [r0, #0x100]
        /* S5P_MPLL_CON */
        ldr     r1, =0x80590201         @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
-       str     r1, [r6, #0x104]
+       str     r1, [r0, #0x104]
        /* S5P_EPLL_CON */
        ldr     r1, =0x80870303         @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
-       str     r1, [r6, #0x108]
+       str     r1, [r0, #0x108]
        /* S5P_HPLL_CON */
        ldr     r1, =0x80600603         @ SDIV 3, PDIV 6, MDIV 96
-       str     r1, [r6, #0x10C]
+       str     r1, [r0, #0x10C]
        b       200f
 110:
        /* Set Lock Time */
        ldr     r1, =0xe10                      @ Locktime : 0xe10 = 3600
-       str     r1, [r6, #0x000]                @ S5P_APLL_LOCK
-       str     r1, [r6, #0x008]                @ S5P_MPLL_LOCK
-       str     r1, [r6, #0x010]                @ S5P_EPLL_LOCK
-       str     r1, [r6, #0x020]                @ S5P_VPLL_LOCK
+       str     r1, [r0, #0x000]                @ S5PC110_APLL_LOCK
+       str     r1, [r0, #0x008]                @ S5PC110_MPLL_LOCK
+       str     r1, [r0, #0x010]                @ S5PC110_EPLL_LOCK
+       str     r1, [r0, #0x020]                @ S5PC110_VPLL_LOCK
 
        /* S5P_APLL_CON */
 #ifdef CONFIG_CLK_667_166_83
@@ -259,20 +259,20 @@ system_clock_init:
 #error you should set the correct clock configuration
 #endif
        ldr     r1, =0x80C80601
-       str     r1, [r6, #0x100]
+       str     r1, [r0, #0x100]
        /* S5P_MPLL_CON */
        ldr     r1, =0x80590201         @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
-       str     r1, [r6, #0x108]
+       str     r1, [r0, #0x108]
        /* S5P_EPLL_CON */
        ldr     r1, =0x80870303         @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
-       str     r1, [r6, #0x110]
+       str     r1, [r0, #0x110]
        /* S5P_VPLL_CON */
        ldr     r1, =0x80600603         @ SDIV 3, PDIV 6, MDIV 96
-       str     r1, [r6, #0x120]
+       str     r1, [r0, #0x120]
 
 200:
        /* Set Clock divider */
-       ldr     r1, [r6, #0x300]
+       ldr     r1, [r0, #0x300]
        ldr     r2, =0x00003fff
        bic     r1, r1, r2
 #ifdef CONFIG_CLK_800_166_66
@@ -285,17 +285,17 @@ system_clock_init:
        ldr     r2, =0x00011301
 #endif
        orr     r1, r1, r2
-       str     r1, [r6, #0x300]
-       ldr     r1, [r6, #0x304]
+       str     r1, [r0, #0x300]
+       ldr     r1, [r0, #0x304]
        ldr     r2, =0x00011110
        orr     r1, r1, r2
-       str     r1, [r6, #0x304]
+       str     r1, [r0, #0x304]
        ldr     r1, =0x00000001
-       str     r1, [r6, #0x308]
+       str     r1, [r0, #0x308]
 
        /* Set Source Clock */
        ldr     r1, =0x1111                     @ A, M, E, HPLL Muxing
-       str     r1, [r6, #0x200]                @ S5P_CLK_SRC0
+       str     r1, [r0, #0x200]                @ S5PC1XX_CLK_SRC0
 
        /* wait at least 200us to stablize all clock */
        mov     r2, #0x10000

diff --git a/board/samsung/universal/mem_setup.S b/board/samsung/universal/mem_setup.S
index 19bfe0f..f30cf5a 100644 (file)
--- a/board/samsung/universal/mem_setup.S
+++ b/board/samsung/universal/mem_setup.S
@@ -27,17 +27,6 @@
 
        .globl mem_ctrl_asm_init
 mem_ctrl_asm_init:
-       ldr     r7, =0xC100
-       ldr     r8, =0xC100
-       /* Read CPU ID */
-       ldr     r2, =S5PC1XX_PRO_ID
-       ldr     r0, [r2]
-       mov     r1, #0x00010000
-       and     r0, r0, r1
-       cmp     r0, r5
-       beq     100f
-       ldr     r8, =0xC110
-100:
        cmp     r7, r8
        ldreq   r6, =S5PC100_DMC_BASE                   @ 0xE6000000
        ldrne   r6, =S5PC110_DMC0_BASE                  @ 0xF0000000

diff --git a/board/samsung/universal/onenand.c b/board/samsung/universal/onenand.c
index 67655b0..97a0532 100644 (file)
--- a/board/samsung/universal/onenand.c
+++ b/board/samsung/universal/onenand.c
@@ -27,6 +27,16 @@ static inline void onenand_write_reg(int value, int offset)
        writel(value, CONFIG_SYS_ONENAND_BASE + offset);
 }
 
+static int s5pc1xx_clock_read(int offset)
+{
+       return readl(S5PC1XX_CLOCK_BASE + offset);
+}
+
+static void s5pc1xx_clock_write(int value, int offset)
+{
+       writel(value, S5PC1XX_CLOCK_BASE + offset);
+}
+
 void onenand_board_init(struct mtd_info *mtd)
 {
        struct onenand_chip *this = mtd->priv;
@@ -38,35 +48,35 @@ void onenand_board_init(struct mtd_info *mtd)
                this->base = (void *)0xB0000000;
 
        /* D0 Domain system 1 clock gating */
-       value = readl(S5P_CLOCK_BASE + S5P_CLK_GATE_D00_OFFSET);
+       value = s5pc1xx_clock_read(S5P_CLK_GATE_D00_OFFSET);
        value &= ~(1 << 2);             /* CFCON */
        value |= (1 << 2);
-       writel(value, S5P_CLOCK_BASE + S5P_CLK_GATE_D00_OFFSET);
+       s5pc1xx_clock_write(value, S5P_CLK_GATE_D00_OFFSET);
 
        /* D0 Domain memory clock gating */
-       value = readl(S5P_CLOCK_BASE + S5P_CLK_GATE_D01_OFFSET);
+       value = s5pc1xx_clock_read(S5P_CLK_GATE_D01_OFFSET);
        value &= ~(1 << 2);             /* CLK_ONENANDC */
        value |= (1 << 2);
-       writel(value, S5P_CLOCK_BASE + S5P_CLK_GATE_D01_OFFSET);
+       s5pc1xx_clock_write(value, S5P_CLK_GATE_D01_OFFSET);
 
        /* System Special clock gating */
-       value = readl(S5P_CLOCK_BASE + S5P_CLK_GATE_SCLK0_OFFSET);
+       value = s5pc1xx_clock_read(S5P_CLK_GATE_SCLK0_OFFSET);
        value &= ~(1 << 2);             /* OneNAND */
        value |= (1 << 2);
-       writel(value, S5P_CLOCK_BASE + S5P_CLK_GATE_SCLK0_OFFSET);
+       s5pc1xx_clock_write(value, S5P_CLK_GATE_SCLK0_OFFSET);
 
-       value = readl(S5P_CLOCK_BASE + S5P_CLK_SRC0_OFFSET);
+       value = s5pc1xx_clock_read(S5P_CLK_SRC0_OFFSET);
        value &= ~(1 << 24);            /* MUX_1nand: 0 from HCLKD0 */
 //     value |= (1 << 24);             /* MUX_1nand: 1 from DIV_D1_BUS */
        value &= ~(1 << 20);            /* MUX_HREF: 0 from FIN_27M */
-       writel(value, S5P_CLOCK_BASE + S5P_CLK_SRC0_OFFSET);
+       s5pc1xx_clock_write(value, S5P_CLK_SRC0_OFFSET);
 
-       value = readl(S5P_CLOCK_BASE + S5P_CLK_DIV1_OFFSET);
+       value = s5pc1xx_clock_read(S5P_CLK_DIV1_OFFSET);
 //     value &= ~(3 << 20);            /* DIV_1nand: 1 / (ratio+1) */
 //     value |= (0 << 20);             /* ratio = 1 */
        value &= ~(3 << 16);
        value |= (1 << 16);
-       writel(value, S5P_CLOCK_BASE + S5P_CLK_DIV1_OFFSET);
+       s5pc1xx_clock_write(value, S5P_CLK_DIV1_OFFSET);
 
        if (cpu_is_s5pc100()) {
                onenand_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET);

diff --git a/include/asm-arm/arch-s5pc1xx/cpu.h b/include/asm-arm/arch-s5pc1xx/cpu.h
index 0f8fa3f..f4df890 100644 (file)
--- a/include/asm-arm/arch-s5pc1xx/cpu.h
+++ b/include/asm-arm/arch-s5pc1xx/cpu.h
@@ -29,7 +29,7 @@
 #define S5PC1XX_ADDR_BASE      0xe0000000
 #define S5P_ADDR(x)            (S5PC1XX_ADDR_BASE + (x))
 
-#define S5P_PA_CLK             S5P_ADDR(0x00100000)    /* Clock Base */
+#define S5PC1XX_CLOCK_BASE     0xE0100000
 #define S5P_PA_PWR             S5P_ADDR(0x00108000)    /* Power Base */
 #define S5P_PA_CLK_OTHERS      S5P_ADDR(0x00200000)    /* Clock Others Base */