#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
MachineFunction *MF;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
+ RegisterClassInfo RegClassInfo;
std::vector<SmallVector<int, 1>> AliasMap;
const unsigned NumRegs;
LiveReg *LiveRegs;
// max clearance or clearance higher than Pref.
unsigned MaxClearance = 0;
unsigned MaxClearanceReg = OriginalReg;
- for (auto Reg : OpRC->getRegisters()) {
+ ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
+ for (auto Reg : Order) {
assert(AliasMap[Reg].size() == 1 &&
"Reg is expected to be mapped to a single index");
int RCrx = *regIndices(Reg).begin();
MF = &mf;
TII = MF->getSubtarget().getInstrInfo();
TRI = MF->getSubtarget().getRegisterInfo();
+ RegClassInfo.runOnMachineFunction(mf);
LiveRegs = nullptr;
assert(NumRegs == RC->getNumRegs() && "Bad regclass");
--- /dev/null
+; RUN: llc < %s -mtriple=i386-linux -mattr=+avx | FileCheck %s
+
+; In i386 there are only 8 XMMs (xmm0-xmm7), make sure we we are not creating illegal XMM
+define float @only_xmm0_7(i32 %arg) {
+top:
+ tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"()
+ tail call void asm sideeffect "", "~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"()
+ %tmp1 = sitofp i32 %arg to float
+ ret float %tmp1
+;CHECK-LABEL:@only_xmm0_7
+;CHECK: vcvtsi2ssl {{.*}}, {{%xmm[0-7]+}}, {{%xmm[0-7]+}}
+}