<&clkc CLKID_SD_EMMC_C_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV2P5>,
- <&clkc CLKID_GP0_PLL>,
<&xtal>;
- clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";
+ clock-names = "core","clkin0","clkin1","clkin2","xtal";
bus-width = <8>;
cap-sd-highspeed;
sd_emmc_b: sdio@ffe05000 {
status = "okay";
- compatible = "amlogic, meson-mmc-tl1";
+ compatible = "amlogic, meson-mmc-tm2";
reg = <0xffe05000 0x800>;
interrupts = <0 190 4>;
/* sd_emmc_b: sd@ffe05000 {
* status = "okay";
- * compatible = "amlogic, meson-mmc-tl1";
+ * compatible = "amlogic, meson-mmc-tm2";
* reg = <0xffe05000 0x800>;
* interrupts = <0 190 1>;
*
"MMC_CAP_1_8V_DDR",
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
- "MMC_CAP_CMD23",
- "MMC_CAP_DRIVER_TYPE_D";
- //caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
+ "MMC_CAP_CMD23";
+ caps2 = "MMC_CAP2_HS200";
+ /* "MMC_CAP2_HS400";*/
f_min = <400000>;
- f_max = <50000000>;
+ f_max = <200000000>;
};
};
sd_emmc_b: sd@ffe05000 {
status = "okay";
- compatible = "amlogic, meson-mmc-tl1";
+ compatible = "amlogic, meson-mmc-tm2";
reg = <0xffe05000 0x800>;
interrupts = <0 190 1>;
"MMC_CAP_MMC_HIGHSPEED",
"MMC_CAP_SD_HIGHSPEED",
"MMC_CAP_NONREMOVABLE",
- /*"MMC_CAP_1_8V_DDR",*/
+ "MMC_CAP_1_8V_DDR",
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
"MMC_CAP_CMD23";
- //caps2 = "MMC_CAP2_HS200";
+ caps2 = "MMC_CAP2_HS200";
/* "MMC_CAP2_HS400";*/
f_min = <400000>;
- f_max = <50000000>;
+ f_max = <200000000>;
};
};
sd_emmc_b: sd@ffe05000 {
status = "okay";
- compatible = "amlogic, meson-mmc-tl1";
+ compatible = "amlogic, meson-mmc-tm2";
reg = <0xffe05000 0x800>;
interrupts = <0 190 1>;
<&clkc CLKID_SD_EMMC_C_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV2P5>,
- <&clkc CLKID_GP0_PLL>,
<&xtal>;
- clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";
+ clock-names = "core","clkin0","clkin1","clkin2","xtal";
bus-width = <8>;
cap-sd-highspeed;
sd_emmc_b: sdio@ffe05000 {
status = "okay";
- compatible = "amlogic, meson-mmc-tl1";
+ compatible = "amlogic, meson-mmc-tm2";
reg = <0x0 0xffe05000 0x0 0x800>;
interrupts = <0 190 4>;
};
/* sd_emmc_b: sd@ffe05000 {
* status = "okay";
- * compatible = "amlogic, meson-mmc-tl1";
+ * compatible = "amlogic, meson-mmc-tm2";
* reg = <0xffe05000 0x800>;
* interrupts = <0 190 1>;
*
"MMC_CAP_1_8V_DDR",
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
- "MMC_CAP_CMD23",
- "MMC_CAP_DRIVER_TYPE_D";
- //caps2 = "MMC_CAP2_HS200"; /* "MMC_CAP2_HS400";*/
+ "MMC_CAP_CMD23";
+ caps2 = "MMC_CAP2_HS200";
+ /* "MMC_CAP2_HS400";*/
f_min = <400000>;
- f_max = <50000000>;
+ f_max = <200000000>;
};
};
/dts-v1/;
#include "mesontm2.dtsi"
-#include "partition_mbox_normal.dtsi"
+#include "partition_mbox_normal_P_32.dtsi"
/ {
model = "Amlogic TM2 T962E2 AB319";
"MMC_CAP_MMC_HIGHSPEED",
"MMC_CAP_SD_HIGHSPEED",
"MMC_CAP_NONREMOVABLE",
- /*"MMC_CAP_1_8V_DDR",*/
+ "MMC_CAP_1_8V_DDR",
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
"MMC_CAP_CMD23";
- /*caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";*/
+ caps2 = "MMC_CAP2_HS200";
+ /* "MMC_CAP2_HS400";*/
f_min = <400000>;
- f_max = <50000000>;
+ f_max = <200000000>;
};
};
sd_emmc_b: sd@ffe05000 {
status = "okay";
- compatible = "amlogic, meson-mmc-tl1";
+ compatible = "amlogic, meson-mmc-tm2";
reg = <0x0 0xffe05000 0x0 0x800>;
interrupts = <0 190 1>;
#include "tl1.h"
PNAME(sd_emmc_parent_names) = { "xtal", "fclk_div2",
- "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll3", "gp0_pll" };
+ "fclk_div3", "fclk_div5", "fclk_div2p5", "mpll2", "mpll3", "gp0_pll" };
/*sd_emmc B*/
static MUX(sd_emmc_p0_mux_B, HHI_SD_EMMC_CLK_CNTL, 0x7, 25,
sd_emmc_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
host->mux_parent[0]);
if (ret)
pr_warn("set comp0 as mux_clk parent error\n");
- } else if (((host->data->chip_type == MMC_CHIP_TL1)
+ } else if (((host->data->chip_type >= MMC_CHIP_TL1)
|| (host->data->chip_type == MMC_CHIP_G12B))
&& (clk_ios >= 166000000)) {
src0_clk = devm_clk_get(host->dev, "clkin2");