drm/amdgpu: enable gfx eop interrupt per gfx pipe
authorHawking Zhang <Hawking.Zhang@amd.com>
Mon, 11 Mar 2019 14:04:44 +0000 (22:04 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 21 Jun 2019 02:24:54 +0000 (21:24 -0500)
Navi10 has 2 gfx pipe and need to enable gfx eop interrupt
per pipe, instead of enable eop int for all gfx pipes at one
time.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

index 79cee38..53c2f55 100644 (file)
@@ -213,7 +213,8 @@ struct amdgpu_atif;
 struct kfd_vm_fault_info;
 
 enum amdgpu_cp_irq {
-       AMDGPU_CP_IRQ_GFX_EOP = 0,
+       AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
+       AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
        AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
        AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
        AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
index c0cb244..0745370 100644 (file)
@@ -3113,7 +3113,7 @@ static int gfx_v6_0_sw_init(void *handle)
                ring->ring_obj = NULL;
                sprintf(ring->name, "gfx");
                r = amdgpu_ring_init(adev, ring, 1024,
-                                    &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
+                                    &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
                if (r)
                        return r;
        }
@@ -3348,7 +3348,7 @@ static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
                                            enum amdgpu_interrupt_state state)
 {
        switch (type) {
-       case AMDGPU_CP_IRQ_GFX_EOP:
+       case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
                gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
                break;
        case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
index 4cd1731..bc5ff82 100644 (file)
@@ -4460,7 +4460,7 @@ static int gfx_v7_0_sw_init(void *handle)
                ring->ring_obj = NULL;
                sprintf(ring->name, "gfx");
                r = amdgpu_ring_init(adev, ring, 1024,
-                                    &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
+                                    &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
                if (r)
                        return r;
        }
@@ -4797,7 +4797,7 @@ static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
                                            enum amdgpu_interrupt_state state)
 {
        switch (type) {
-       case AMDGPU_CP_IRQ_GFX_EOP:
+       case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
                gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
                break;
        case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
index c9cc7a2..a4fec80 100644 (file)
@@ -2005,7 +2005,7 @@ static int gfx_v8_0_sw_init(void *handle)
                }
 
                r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
-                                    AMDGPU_CP_IRQ_GFX_EOP);
+                                    AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
                if (r)
                        return r;
        }
@@ -6533,7 +6533,7 @@ static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
                                            enum amdgpu_interrupt_state state)
 {
        switch (type) {
-       case AMDGPU_CP_IRQ_GFX_EOP:
+       case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
                gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
                break;
        case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
index 76a1211..e0f3014 100644 (file)
@@ -1721,7 +1721,7 @@ static int gfx_v9_0_sw_init(void *handle)
                ring->use_doorbell = true;
                ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
                r = amdgpu_ring_init(adev, ring, 1024,
-                                    &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
+                                    &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
                if (r)
                        return r;
        }
@@ -5025,7 +5025,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
                                            enum amdgpu_interrupt_state state)
 {
        switch (type) {
-       case AMDGPU_CP_IRQ_GFX_EOP:
+       case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
                gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
                break;
        case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: