Fix 33524; SSE5 vectorized int->long conversions are broken

From-SVN: r128768

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9a4d954..7fe7828 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2007-09-25  Michael Meissner  <michael.meissner@amd.com>
+
+       PR c/33524
+       * config/i386/i386.c (ix86_expand_sse5_unpack): Change to call
+       gen_sse5_pperm_sign_v4si_v2di and gen_sse5_pperm_zero_v4si_v2di
+       for vector int32 -> int64 conversions.  Don't write beyond the end
+       of the allocated vector for int32 -> int64 conversions.
+
 2007-09-25  Revital Eres  <eres@il.ibm.com>
 
        * config/rs6000/paired.h (paired_sel): New.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index a9ca27b..e208fb4 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -13542,15 +13542,15 @@ ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
       for (i = 0; i < 16; i++)
        RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
 
-      for (i = 0; i < 4; i++)
+      for (i = 0; i < 2; i++)
        RTVEC_ELT (vs, i) = GEN_INT (i + h2);
 
       p = gen_rtx_PARALLEL (VOIDmode, vs);
       x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
       if (unsigned_p)
-       emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
+       emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
       else
-       emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
+       emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
       break;
 
     default:

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a4c4923..ed4ce25 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2007-09-25  Michael Meissner  <michael.meissner@amd.com>
+
+       PR c/33524
+       * gcc.target/i386/sse5-convert.c: New file, test int->long
+       vectorized conversions.
+
 2007-09-25  Revital Eres  <eres@il.ibm.com>
 
        * testsuite/gcc.target/powerpc/ppc-paired.c (paired_sel): Add.

diff --git a/gcc/testsuite/gcc.target/i386/sse5-convert.c b/gcc/testsuite/gcc.target/i386/sse5-convert.c
new file mode 100644 (file)
index 0000000..0dfdc3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse5-convert.c
@@ -0,0 +1,26 @@
+/* Test that the compiler properly optimizes vector SI->DI conversions.  This
+   was a bug in the initial SSE5 code.  */
+
+/* { dg-do compile { target x86_64-*-*} } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+/* This is PR c/33524 */
+
+typedef long long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+union {
+  signed   int   si[SIZE];
+  signed   long  sl[SIZE];
+  __m128i        align;
+} a, b;
+
+void conv_sign_int_sign_long (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.sl[i] = b.si[i];
+}
+
+/* { dg-final { scan-assembler "pperm" } } */