arm64: dts: mediatek: mt6795: Create soc bus node and move mmio devices

MMIO devices should be inside of a soc bus node, as it's done for the
vast majority of ARM64 devicetrees, and for almost all MTK devicetrees.
Create a simple-bus soc node and move all devices with a MMIO address
space in there.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220609112303.117928-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index c85659d..167f90b 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -117,59 +117,66 @@
                             (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
        };
 
-       sysirq: intpol-controller@10200620 {
-               compatible = "mediatek,mt6795-sysirq",
-                            "mediatek,mt6577-sysirq";
-               interrupt-controller;
-               #interrupt-cells = <3>;
-               interrupt-parent = <&gic>;
-               reg = <0 0x10200620 0 0x20>;
-       };
+       soc {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               compatible = "simple-bus";
+               ranges;
+
+               sysirq: intpol-controller@10200620 {
+                       compatible = "mediatek,mt6795-sysirq",
+                                    "mediatek,mt6577-sysirq";
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+                       interrupt-parent = <&gic>;
+                       reg = <0 0x10200620 0 0x20>;
+               };
 
-       gic: interrupt-controller@10221000 {
-               compatible = "arm,gic-400";
-               #interrupt-cells = <3>;
-               interrupt-parent = <&gic>;
-               interrupt-controller;
-               reg = <0 0x10221000 0 0x1000>,
-                     <0 0x10222000 0 0x2000>,
-                     <0 0x10224000 0 0x2000>,
-                     <0 0x10226000 0 0x2000>;
-       };
+               gic: interrupt-controller@10221000 {
+                       compatible = "arm,gic-400";
+                       #interrupt-cells = <3>;
+                       interrupt-parent = <&gic>;
+                       interrupt-controller;
+                       reg = <0 0x10221000 0 0x1000>,
+                             <0 0x10222000 0 0x2000>,
+                             <0 0x10224000 0 0x2000>,
+                             <0 0x10226000 0 0x2000>;
+               };
 
-       uart0: serial@11002000 {
-               compatible = "mediatek,mt6795-uart",
-                            "mediatek,mt6577-uart";
-               reg = <0 0x11002000 0 0x400>;
-               interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&uart_clk>;
-               status = "disabled";
-       };
+               uart0: serial@11002000 {
+                       compatible = "mediatek,mt6795-uart",
+                                    "mediatek,mt6577-uart";
+                       reg = <0 0x11002000 0 0x400>;
+                       interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
 
-       uart1: serial@11003000 {
-               compatible = "mediatek,mt6795-uart",
-                            "mediatek,mt6577-uart";
-               reg = <0 0x11003000 0 0x400>;
-               interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&uart_clk>;
-               status = "disabled";
-       };
+               uart1: serial@11003000 {
+                       compatible = "mediatek,mt6795-uart",
+                                    "mediatek,mt6577-uart";
+                       reg = <0 0x11003000 0 0x400>;
+                       interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
 
-       uart2: serial@11004000 {
-               compatible = "mediatek,mt6795-uart",
-                            "mediatek,mt6577-uart";
-               reg = <0 0x11004000 0 0x400>;
-               interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&uart_clk>;
-               status = "disabled";
-       };
+               uart2: serial@11004000 {
+                       compatible = "mediatek,mt6795-uart",
+                                    "mediatek,mt6577-uart";
+                       reg = <0 0x11004000 0 0x400>;
+                       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
 
-       uart3: serial@11005000 {
-               compatible = "mediatek,mt6795-uart",
-                            "mediatek,mt6577-uart";
-               reg = <0 0x11005000 0 0x400>;
-               interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&uart_clk>;
-               status = "disabled";
+               uart3: serial@11005000 {
+                       compatible = "mediatek,mt6795-uart",
+                                    "mediatek,mt6577-uart";
+                       reg = <0 0x11005000 0 0x400>;
+                       interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
        };
 };