Enable legacy jit for x86

Commit migrated from https://github.com/dotnet/coreclr/commit/2242b2ec7caa929b862c63bfbdd08604b5ce69b4

diff --git a/src/coreclr/src/jit/CMakeLists.txt b/src/coreclr/src/jit/CMakeLists.txt
index e2a9ca6..b34cf63 100644 (file)
--- a/src/coreclr/src/jit/CMakeLists.txt
+++ b/src/coreclr/src/jit/CMakeLists.txt
@@ -238,6 +238,7 @@ if ((CLR_CMAKE_PLATFORM_ARCH_I386 OR CLR_CMAKE_PLATFORM_ARCH_AMD64) AND WIN32)
 endif ()
 
 if (CLR_CMAKE_PLATFORM_ARCH_I386 AND WIN32)
+    add_subdirectory(legacyjit)
     # On Windows x86, build altjit generating Windows/ARM32 code using LEGACY_BACKEND.
     # (Note: we could also create linuxlegacynonjit for generating Linux/ARM32 code using LEGACY_BACKEND, if needed.)
     add_subdirectory(legacynonjit)

diff --git a/src/coreclr/src/jit/DIRS.proj b/src/coreclr/src/jit/DIRS.proj
index 12ea52f..539743c 100644 (file)
--- a/src/coreclr/src/jit/DIRS.proj
+++ b/src/coreclr/src/jit/DIRS.proj
@@ -26,7 +26,7 @@
   <ItemGroup Condition="'$(BuildExePhase)' == '1' and '$(BuildProjectName)' != 'CoreSys'">
 
     <!-- Build the "FrankenJit" (RyuJIT front-end, legacy back-end) and "FrankenAltjit". These can't conflict with the names of the JIT32 directory outputs. -->
-    <ProjectFile Condition="'$(BuildArchitecture)' == 'arm'"  Include="frankenjit\frankenjit.nativeproj" />
+    <ProjectFile Condition="'$(BuildArchitecture)' == 'i386' or '$(BuildArchitecture)' == 'arm'"  Include="frankenjit\frankenjit.nativeproj" />
     <ProjectFile Condition="'$(BuildArchitecture)' == 'i386'" Include="frankenaltjit\frankenaltjit.nativeproj" />
 
     <!-- This might be useful, to help make sure JIT devs build all configurations of the JIT (including crossgen), but

diff --git a/src/coreclr/src/jit/emit.h b/src/coreclr/src/jit/emit.h
index a925f1f..ce91e2d 100644 (file)
--- a/src/coreclr/src/jit/emit.h
+++ b/src/coreclr/src/jit/emit.h
@@ -828,6 +828,8 @@ protected:
         unsigned _idCnsReloc : 1; // LargeCns is an RVA and needs reloc tag
         unsigned _idDspReloc : 1; // LargeDsp is an RVA and needs reloc tag
 
+#define ID_EXTRA_RELOC_BITS (2)
+
 #define ID_EXTRA_REG_BITS (0)
 
 #define ID_EXTRA_BITS (ID_EXTRA_BITFIELD_BITS + ID_EXTRA_RELOC_BITS + ID_EXTRA_REG_BITS)

diff --git a/src/coreclr/src/jit/emitxarch.cpp b/src/coreclr/src/jit/emitxarch.cpp
index 5a0abe7..b651782 100644 (file)
--- a/src/coreclr/src/jit/emitxarch.cpp
+++ b/src/coreclr/src/jit/emitxarch.cpp
@@ -209,6 +209,7 @@ emitter::code_t emitter::AddVexPrefix(instruction ins, code_t code, emitAttr att
 // Returns true if this instruction, for the given EA_SIZE(attr), will require a REX.W prefix
 bool TakesRexWPrefix(instruction ins, emitAttr attr)
 {
+#ifndef LEGACY_BACKEND
     // Because the current implementation of AVX does not have a way to distinguish between the register
     // size specification (128 vs. 256 bits) and the operand size specification (32 vs. 64 bits), where both are
     // required, the instruction must be created with the register size attribute (EA_16BYTE or EA_32BYTE),
@@ -217,6 +218,7 @@ bool TakesRexWPrefix(instruction ins, emitAttr attr)
     {
         return true;
     }
+#endif // !LEGACY_BACKEND
 #ifdef _TARGET_AMD64_
     // movsx should always sign extend out to 8 bytes just because we don't track
     // whether the dest should be 4 bytes or 8 bytes (attr indicates the size
@@ -359,10 +361,10 @@ emitter::code_t emitter::AddRexWPrefix(instruction ins, code_t code)
         assert(hasVexPrefix(code));
 
         // W-bit is the only bit that is added in non bit-inverted form.
-        return code | 0x00008000000000ULL;
+        return emitter::code_t(code | 0x00008000000000ULL);
     }
 #ifdef _TARGET_AMD64_
-    return code | 0x4800000000ULL;
+    return emitter::code_t(code | 0x4800000000ULL);
 #else
     assert(!"UNREACHED");
     return code;

diff --git a/src/coreclr/src/jit/legacyjit/CMakeLists.txt b/src/coreclr/src/jit/legacyjit/CMakeLists.txt
new file mode 100644 (file)
index 0000000..84fb42e
--- /dev/null
+++ b/src/coreclr/src/jit/legacyjit/CMakeLists.txt
@@ -0,0 +1,63 @@
+project(legacyjit)
+
+add_definitions(-DLEGACY_BACKEND)
+add_definitions(-DALT_JIT)
+add_definitions(-DFEATURE_NO_HOST)
+add_definitions(-DSELF_NO_HOST)
+add_definitions(-DFEATURE_READYTORUN_COMPILER)
+remove_definitions(-DFEATURE_MERGE_JIT_AND_ENGINE)
+
+# No SIMD in legacy back-end.
+remove_definitions(-DFEATURE_SIMD)
+remove_definitions(-DFEATURE_AVX_SUPPORT)
+
+if(WIN32)
+  add_definitions(-DFX_VER_INTERNALNAME_STR=legacyjit.dll)
+endif(WIN32)
+
+add_library_clr(legacyjit
+   SHARED
+   ${SHARED_LIB_SOURCES}
+   ${JIT_ARCH_SOURCES}
+)
+
+add_dependencies(legacyjit jit_exports)
+
+set_property(TARGET legacyjit APPEND_STRING PROPERTY LINK_FLAGS ${JIT_EXPORTS_LINKER_OPTION})
+set_property(TARGET legacyjit APPEND_STRING PROPERTY LINK_DEPENDS ${JIT_EXPORTS_FILE})
+
+set(RYUJIT_LINK_LIBRARIES
+   utilcodestaticnohost
+   gcinfo
+)
+
+if(CLR_CMAKE_PLATFORM_UNIX)
+    list(APPEND RYUJIT_LINK_LIBRARIES
+       mscorrc_debug
+       coreclrpal
+       palrt
+    )
+else()
+    list(APPEND RYUJIT_LINK_LIBRARIES
+       ${STATIC_MT_CRT_LIB}
+       ${STATIC_MT_VCRT_LIB}
+       kernel32.lib
+       advapi32.lib
+       ole32.lib
+       oleaut32.lib
+       uuid.lib
+       user32.lib
+       version.lib
+       shlwapi.lib
+       bcrypt.lib
+       crypt32.lib
+       RuntimeObject.lib
+    )
+endif(CLR_CMAKE_PLATFORM_UNIX)
+
+target_link_libraries(legacyjit
+   ${RYUJIT_LINK_LIBRARIES}
+)
+
+# add the install targets
+install_clr(legacyjit)
\ No newline at end of file

diff --git a/src/coreclr/src/jit/stackfp.cpp b/src/coreclr/src/jit/stackfp.cpp
index e6d4c9e..594c73e 100644 (file)
--- a/src/coreclr/src/jit/stackfp.cpp
+++ b/src/coreclr/src/jit/stackfp.cpp
@@ -411,8 +411,8 @@ void CodeGen::genCodeForPrologStackFP()
 
     if (pState && pState->m_uStackSize)
     {
-        VARSET_TP VARSET_INIT_NOCOPY(liveEnregIn, VarSetOps::Intersection(compiler, compiler->fgFirstBB->bbLiveIn,
-                                                                          compiler->optAllFPregVars));
+        VARSET_TP liveEnregIn(
+            VarSetOps::Intersection(compiler, compiler->fgFirstBB->bbLiveIn, compiler->optAllFPregVars));
         unsigned i;
 
 #ifdef DEBUG
@@ -1066,8 +1066,7 @@ void CodeGen::genSetupStateStackFP(BasicBlock* block)
     }
 
     // Update liveset and lock enregistered live vars on entry
-    VARSET_TP VARSET_INIT_NOCOPY(liveSet,
-                                 VarSetOps::Intersection(compiler, block->bbLiveIn, compiler->optAllFPregVars));
+    VARSET_TP liveSet(VarSetOps::Intersection(compiler, block->bbLiveIn, compiler->optAllFPregVars));
 
     if (!VarSetOps::IsEmpty(compiler, liveSet))
     {
@@ -2912,7 +2911,7 @@ void CodeGen::genCondJumpLngStackFP(GenTreePtr cond, BasicBlock* jumpTrue, Basic
 void CodeGen::genQMarkRegVarTransition(GenTreePtr nextNode, VARSET_VALARG_TP liveset)
 {
     // Kill any vars that may die in the transition
-    VARSET_TP VARSET_INIT_NOCOPY(newLiveSet, VarSetOps::Intersection(compiler, liveset, compiler->optAllFPregVars));
+    VARSET_TP newLiveSet(VarSetOps::Intersection(compiler, liveset, compiler->optAllFPregVars));
 
     regMaskTP liveRegIn = genRegMaskFromLivenessStackFP(newLiveSet);
     genCodeForTransitionFromMask(&compCurFPState, liveRegIn);
@@ -3088,8 +3087,8 @@ void CodeGen::genTableSwitchStackFP(regNumber reg, unsigned jumpCnt, BasicBlock*
     // Only come here when we have to do something special for the FPU stack!
     //
     assert(!compCurFPState.IsEmpty());
-    VARSET_TP VARSET_INIT_NOCOPY(liveInFP, VarSetOps::MakeEmpty(compiler));
-    VARSET_TP VARSET_INIT_NOCOPY(liveOutFP, VarSetOps::MakeEmpty(compiler));
+    VARSET_TP liveInFP(VarSetOps::MakeEmpty(compiler));
+    VARSET_TP liveOutFP(VarSetOps::MakeEmpty(compiler));
     for (unsigned i = 0; i < jumpCnt; i++)
     {
         VarSetOps::Assign(compiler, liveInFP, jumpTab[i]->bbLiveIn);
@@ -3687,7 +3686,7 @@ regNumber Compiler::raRegForVarStackFP(unsigned varTrackedIndex)
 
 void Compiler::raAddPayloadStackFP(VARSET_VALARG_TP maskArg, unsigned weight)
 {
-    VARSET_TP VARSET_INIT_NOCOPY(mask, VarSetOps::Intersection(this, maskArg, optAllFloatVars));
+    VARSET_TP mask(VarSetOps::Intersection(this, maskArg, optAllFloatVars));
     if (VarSetOps::IsEmpty(this, mask))
     {
         return;
@@ -3854,7 +3853,7 @@ void Compiler::raEnregisterVarsPrePassStackFP()
     //
     //
     //
-    VARSET_TP VARSET_INIT_NOCOPY(blockLiveOutFloats, VarSetOps::MakeEmpty(this));
+    VARSET_TP blockLiveOutFloats(VarSetOps::MakeEmpty(this));
     for (block = fgFirstBB; block; block = block->bbNext)
     {
         compCurBB = block;
@@ -3936,7 +3935,7 @@ void Compiler::raEnregisterVarsPrePassStackFP()
             }
         }
 
-        VARSET_TP VARSET_INIT(this, liveSet, block->bbLiveIn);
+        VARSET_TP liveSet(VarSetOps::MakeCopy(this, block->bbLiveIn));
         for (GenTreePtr stmt = block->FirstNonPhiDef(); stmt; stmt = stmt->gtNext)
         {
             assert(stmt->gtOper == GT_STMT);
@@ -4128,7 +4127,7 @@ void Compiler::raEnregisterVarsPostPassStackFP()
         }
         */
 
-        VARSET_TP VARSET_INIT(this, lastlife, block->bbLiveIn);
+        VARSET_TP lastlife(VarSetOps::MakeCopy(this, block->bbLiveIn));
         for (GenTreePtr stmt = block->FirstNonPhiDef(); stmt; stmt = stmt->gtNext)
         {
             assert(stmt->gtOper == GT_STMT);
@@ -4438,7 +4437,7 @@ void Compiler::raEnregisterVarsStackFP()
 
         // Create interferences with other variables.
         assert(VarSetOps::IsEmpty(this, VarSetOps::Diff(this, raLclRegIntfFloat[(int)reg], optAllFloatVars)));
-        VARSET_TP VARSET_INIT_NOCOPY(intfFloats, VarSetOps::Intersection(this, lvaVarIntf[varIndex], optAllFloatVars));
+        VARSET_TP intfFloats(VarSetOps::Intersection(this, lvaVarIntf[varIndex], optAllFloatVars));
 
         VarSetOps::UnionD(this, raLclRegIntfFloat[reg], intfFloats);