Update listing of when SSSE3 and SSE4.1 first became available

SSSE3 was first available on the original Intel Core 2 processors, so
add the "Merom" codename. SSE4.1 was available on the 45 nm shrink of
those processors, codename "Penryn", not on the next architecture.

Change-Id: I5fd92db62aa409b7f4e46f9b24d960519177f811
Reviewed-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>

diff --git a/config.tests/arch/arch.cpp b/config.tests/arch/arch.cpp
index da0fe1c..e9530e6 100644 (file)
--- a/config.tests/arch/arch.cpp
+++ b/config.tests/arch/arch.cpp
@@ -182,7 +182,7 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
 " sse3"
 #endif
 #ifdef __SSSE3__
-// Supplemental SSE3, Intel Core 2, AMD "Bulldozer"
+// Supplemental SSE3, Intel Core 2 ("Merom"), AMD "Bulldozer"
 " ssse3"
 #endif
 #ifdef __SSE4A__
@@ -190,7 +190,7 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
 " sse4a"
 #endif
 #ifdef __SSE4_1__
-// SSE 4.1, Intel Core-i7 ("Nehalem"), AMD "Bulldozer"
+// SSE 4.1, Intel Core2 45nm shrink ("Penryn"), AMD "Bulldozer"
 " sse4.1"
 #endif
 #ifdef __SSE4_2__