x86/cpu: Update Hybrids

Give the hybrid thingies their own section, appropriately between Core
and Atom.

Add the Raptor Lake uarch names.

Put Lunar Lake after Arrow Lake per interweb guidance.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20230807150405.828551866@infradead.org

diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 49d40ee..5fcd85f 100644 (file)
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -98,8 +98,6 @@
 #define INTEL_FAM6_ICELAKE_L           0x7E    /* Sunny Cove */
 #define INTEL_FAM6_ICELAKE_NNPI                0x9D    /* Sunny Cove */
 
-#define INTEL_FAM6_LAKEFIELD           0x8A    /* Sunny Cove / Tremont */
-
 #define INTEL_FAM6_ROCKETLAKE          0xA7    /* Cypress Cove */
 
 #define INTEL_FAM6_TIGERLAKE_L         0x8C    /* Willow Cove */
@@ -112,20 +110,24 @@
 #define INTEL_FAM6_GRANITERAPIDS_X     0xAD
 #define INTEL_FAM6_GRANITERAPIDS_D     0xAE
 
+/* "Hybrid" Processors (P-Core/E-Core) */
+
+#define INTEL_FAM6_LAKEFIELD           0x8A    /* Sunny Cove / Tremont */
+
 #define INTEL_FAM6_ALDERLAKE           0x97    /* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_L         0x9A    /* Golden Cove / Gracemont */
 
-#define INTEL_FAM6_RAPTORLAKE          0xB7
+#define INTEL_FAM6_RAPTORLAKE          0xB7    /* Raptor Cove / Enhanced Gracemont */
 #define INTEL_FAM6_RAPTORLAKE_P                0xBA
 #define INTEL_FAM6_RAPTORLAKE_S                0xBF
 
 #define INTEL_FAM6_METEORLAKE          0xAC
 #define INTEL_FAM6_METEORLAKE_L                0xAA
 
-#define INTEL_FAM6_LUNARLAKE_M         0xBD
-
 #define INTEL_FAM6_ARROWLAKE           0xC6
 
+#define INTEL_FAM6_LUNARLAKE_M         0xBD
+
 /* "Small Core" Processors (Atom/E-Core) */
 
 #define INTEL_FAM6_ATOM_BONNELL                0x1C /* Diamondville, Pineview */