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net/mlx5: Fix PBMC register mapping
authorAya Levin <ayal@nvidia.com>
Sun, 4 Apr 2021 09:55:00 +0000 (12:55 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Wed, 7 Apr 2021 04:04:36 +0000 (21:04 -0700)
Add reserved mapping to cover all the register in order to avoid setting
arbitrary values to newer FW which implements the reserved fields.

Fixes: 50b4a3c23646 ("net/mlx5: PPTB and PBMC register firmware command support")
Signed-off-by: Aya Levin <ayal@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
include/linux/mlx5/mlx5_ifc.h patch | blob | history

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 9940070cda8ffeb2a9d542c14029905409091af5..9c68b2da14c637ce74020d909c1a9ea0b963c9a0 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -10200,7 +10200,7 @@ struct mlx5_ifc_pbmc_reg_bits {
 
        struct mlx5_ifc_bufferx_reg_bits buffer[10];
 
-       u8         reserved_at_2e0[0x40];
+       u8         reserved_at_2e0[0x80];
 };
 
 struct mlx5_ifc_qtct_reg_bits {
Domain: System / Kernel;