}
def : InstRW<[ZnWriteLD_F80m], (instrs LD_F80m)>;
-// FBLD.
-def : InstRW<[WriteMicrocoded], (instrs FBLDm)>;
-
// FST(P).
// r.
def : InstRW<[ZnWriteSTr], (instregex "ST_(F|FP)rr")>;
}
def : InstRW<[ZnWriteST_FP80m], (instrs ST_FP80m)>;
-// FBSTP.
-// m80.
-def : InstRW<[WriteMicrocoded], (instrs FBSTPm)>;
-
def ZnWriteFXCH : SchedWriteRes<[ZnFPU]>;
// FXCHG.
// AX.
def : InstRW<[WriteMicrocoded], (instrs FNSTSW16r)>;
-// m16.
-def : InstRW<[WriteMicrocoded], (instrs FNSTSWm)>;
-
// FLDCW.
def : InstRW<[WriteMicrocoded], (instrs FLDCW16m)>;
// FFREE.
def : InstRW<[ZnWriteFPU3], (instregex "FFREE")>;
-// FNSAVE.
-def : InstRW<[WriteMicrocoded], (instrs FSAVEm)>;
-
-// FRSTOR.
-def : InstRW<[WriteMicrocoded], (instrs FRSTORm)>;
-
//-- Arithmetic instructions --//
def ZnWriteFPU3Lat1 : SchedWriteRes<[ZnFPU3]> ;
// FXAM.
def : InstRW<[ZnWriteFPU3Lat1], (instrs XAM_F)>;
-// FPREM.
-def : InstRW<[WriteMicrocoded], (instrs FPREM)>;
-
-// FPREM1.
-def : InstRW<[WriteMicrocoded], (instrs FPREM1)>;
-
-// FRNDINT.
-def : InstRW<[WriteMicrocoded], (instrs FRNDINT)>;
-
-// FSCALE.
-def : InstRW<[WriteMicrocoded], (instrs FSCALE)>;
-
-// FXTRACT.
-def : InstRW<[WriteMicrocoded], (instrs FXTRACT)>;
-
// FNOP.
def : InstRW<[ZnWriteFPU0Lat1], (instrs FNOP)>;
// WAIT.
def : InstRW<[ZnWriteFPU0Lat1], (instrs WAIT)>;
-// FNCLEX.
-def : InstRW<[WriteMicrocoded], (instrs FNCLEX)>;
-
-// FNINIT.
-def : InstRW<[WriteMicrocoded], (instrs FNINIT)>;
-
//=== Integer MMX and XMM Instructions ===//
def ZnWriteFPU013 : SchedWriteRes<[ZnFPU013]> ;
}
def : InstRW<[Zn2WriteLD_F80m], (instrs LD_F80m)>;
-// FBLD.
-def : InstRW<[WriteMicrocoded], (instrs FBLDm)>;
-
// FST(P).
// r.
def : InstRW<[Zn2WriteSTr], (instregex "ST_(F|FP)rr")>;
}
def : InstRW<[Zn2WriteST_FP80m], (instrs ST_FP80m)>;
-// FBSTP.
-// m80.
-def : InstRW<[WriteMicrocoded], (instrs FBSTPm)>;
-
def Zn2WriteFXCH : SchedWriteRes<[Zn2FPU]>;
// FXCHG.
// AX.
def : InstRW<[WriteMicrocoded], (instrs FNSTSW16r)>;
-// m16.
-def : InstRW<[WriteMicrocoded], (instrs FNSTSWm)>;
-
// FLDCW.
def : InstRW<[WriteMicrocoded], (instrs FLDCW16m)>;
// FFREE.
def : InstRW<[Zn2WriteFPU3], (instregex "FFREE")>;
-// FNSAVE.
-def : InstRW<[WriteMicrocoded], (instrs FSAVEm)>;
-
-// FRSTOR.
-def : InstRW<[WriteMicrocoded], (instrs FRSTORm)>;
-
//-- Arithmetic instructions --//
def Zn2WriteFPU3Lat1 : SchedWriteRes<[Zn2FPU3]> ;
// FXAM.
def : InstRW<[Zn2WriteFPU3Lat1], (instrs XAM_F)>;
-// FPREM.
-def : InstRW<[WriteMicrocoded], (instrs FPREM)>;
-
-// FPREM1.
-def : InstRW<[WriteMicrocoded], (instrs FPREM1)>;
-
-// FRNDINT.
-def : InstRW<[WriteMicrocoded], (instrs FRNDINT)>;
-
-// FSCALE.
-def : InstRW<[WriteMicrocoded], (instrs FSCALE)>;
-
-// FXTRACT.
-def : InstRW<[WriteMicrocoded], (instrs FXTRACT)>;
-
// FNOP.
def : InstRW<[Zn2WriteFPU0Lat1], (instrs FNOP)>;
// WAIT.
def : InstRW<[Zn2WriteFPU0Lat1], (instrs WAIT)>;
-// FNCLEX.
-def : InstRW<[WriteMicrocoded], (instrs FNCLEX)>;
-
-// FNINIT.
-def : InstRW<[WriteMicrocoded], (instrs FNINIT)>;
-
//=== Integer MMX and XMM Instructions ===//
def Zn2WriteFPU013 : SchedWriteRes<[Zn2FPU013]> ;