SmallVector<PredCheck, 4> PredTerm;
SmallVector<SmallVector<unsigned,4>, 16> WriteSequences;
SmallVector<SmallVector<unsigned,4>, 16> ReadSequences;
- SmallVector<unsigned, 4> ProcIndices;
+ unsigned ProcIndex = 0;
PredTransition() = default;
- PredTransition(ArrayRef<PredCheck> PT) {
+ PredTransition(ArrayRef<PredCheck> PT, unsigned ProcId) {
PredTerm.assign(PT.begin(), PT.end());
- ProcIndices.assign(1, 0);
- }
- PredTransition(ArrayRef<PredCheck> PT, ArrayRef<unsigned> PIds) {
- PredTerm.assign(PT.begin(), PT.end());
- ProcIndices.assign(PIds.begin(), PIds.end());
+ ProcIndex = ProcId;
}
};
}
static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants,
- ArrayRef<unsigned> ProcIndices) {
+ unsigned ProcId) {
std::vector<Record *> Preds;
for (auto &Variant : Variants) {
if (!Variant.VarOrSeqDef->isSubClassOf("SchedVar"))
continue;
-
- if (ProcIndices[0] && Variant.ProcIdx)
- if (!llvm::count(ProcIndices, Variant.ProcIdx))
- continue;
-
Preds.push_back(Variant.VarOrSeqDef->getValueAsDef("Predicate"));
}
return Preds;
Record *ModelDef = SchedRW.TheDef->getValueAsDef("SchedModel");
VarProcIdx = SchedModels.getProcModel(ModelDef).Index;
}
- // Push each variant. Assign TransVecIdx later.
- const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
- for (Record *VarDef : VarDefs)
- Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0);
- if (VarProcIdx == 0)
- GenericRW = true;
+ if (VarProcIdx == 0 || VarProcIdx == TransVec[TransIdx].ProcIndex) {
+ // Push each variant. Assign TransVecIdx later.
+ const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
+ for (Record *VarDef : VarDefs)
+ Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0);
+ if (VarProcIdx == 0)
+ GenericRW = true;
+ }
}
for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
AI != AE; ++AI) {
Record *ModelDef = (*AI)->getValueAsDef("SchedModel");
AliasProcIdx = SchedModels.getProcModel(ModelDef).Index;
}
+ if (AliasProcIdx && AliasProcIdx != TransVec[TransIdx].ProcIndex)
+ continue;
+ if (!Variants.empty()) {
+ const CodeGenProcModel &PM =
+ *(SchedModels.procModelBegin() + AliasProcIdx);
+ PrintFatalError((*AI)->getLoc(),
+ "Multiple variants defined for processor " +
+ PM.ModelName +
+ " Ensure only one SchedAlias exists per RW.");
+ }
+
const CodeGenSchedRW &AliasRW =
SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
GenericRW = true;
}
std::vector<Record *> AllPreds =
- getAllPredicates(Variants, TransVec[TransIdx].ProcIndices);
+ getAllPredicates(Variants, TransVec[TransIdx].ProcIndex);
for (TransVariant &Variant : Variants) {
// Don't expand variants if the processor models don't intersect.
// A zero processor index means any processor.
- SmallVectorImpl<unsigned> &ProcIndices = TransVec[TransIdx].ProcIndices;
- if (ProcIndices[0] && Variant.ProcIdx) {
- unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(),
- Variant.ProcIdx);
- if (!Cnt)
- continue;
- if (Cnt > 1) {
- const CodeGenProcModel &PM =
- *(SchedModels.procModelBegin() + Variant.ProcIdx);
- PrintFatalError(Variant.VarOrSeqDef->getLoc(),
- "Multiple variants defined for processor " +
- PM.ModelName +
- " Ensure only one SchedAlias exists per RW.");
- }
- }
if (Variant.VarOrSeqDef->isSubClassOf("SchedVar")) {
Record *PredDef = Variant.VarOrSeqDef->getValueAsDef("Predicate");
if (mutuallyExclusive(PredDef, AllPreds, TransVec[TransIdx].PredTerm))
// If this operand transition is reached through a processor-specific alias,
// then the whole transition is specific to this processor.
- if (VInfo.ProcIdx != 0)
- Trans.ProcIndices.assign(1, VInfo.ProcIdx);
-
IdxVec SelectedRWs;
if (VInfo.VarOrSeqDef->isSubClassOf("SchedVar")) {
Record *PredDef = VInfo.VarOrSeqDef->getValueAsDef("Predicate");
// PredTransitions. Remember the first new transition.
unsigned StartIdx = TransVec.size();
bool Subst = false;
- TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndices);
+ assert(Trans.ProcIndex != 0);
+ TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndex);
- assert(!llvm::count(Trans.ProcIndices, 0));
// Visit each original write sequence.
for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
WSI = Trans.WriteSequences.begin(), WSE = Trans.WriteSequences.end();
<< FromSC.Index << ") to "
<< SchedModels.getSchedClass(SCTrans.ToClassIdx).Name << "("
<< SCTrans.ToClassIdx << ") on pred term: (";
- dumpRecVec(Preds); dbgs() << ") on processor indices: (";
- dumpIdxVec(SCTrans.ProcIndices); dbgs() << ")\n");
+ dumpRecVec(Preds);
+ dbgs() << ") on processor (" << SCTrans.ProcIndex << ")\n");
}
// Create a new SchedClass for each variant found by inferFromRW. Pass
static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions,
// Transition should not contain processor indices already assigned to
// InstRWs in this scheduling class.
const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx);
- llvm::copy_if(I->ProcIndices, std::back_inserter(SCTrans.ProcIndices),
- [&FromSC](unsigned PIdx) {
- return !FromSC.InstRWProcIndices.count(PIdx);
- });
- if (SCTrans.ProcIndices.empty())
+ if (FromSC.InstRWProcIndices.count(I->ProcIndex))
continue;
+ SCTrans.ProcIndex = I->ProcIndex;
SCTrans.ToClassIdx =
SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant,
- OperReadsVariant, I->ProcIndices);
+ OperReadsVariant, I->ProcIndex);
// The final PredTerm is unique set of predicates guarding the transition.
RecVec Preds;
for (unsigned ProcId : ProcIndices) {
assert(ProcId != 0);
PerCpuTransVec.push_back(Trans);
- PerCpuTransVec.back().ProcIndices.assign(1, ProcId);
+ PerCpuTransVec.back().ProcIndex = ProcId;
}
return PerCpuTransVec;
}
// of SchedWrites for the current SchedClass.
std::vector<PredTransition> LastTransitions;
LastTransitions.emplace_back();
- LastTransitions.back().ProcIndices.append(ProcIndices.begin(),
- ProcIndices.end());
for (unsigned WriteIdx : OperWrites) {
IdxVec WriteSeq;
if (!Transitions.empty()) {
dbgs() << "\n Transitions for Proc ";
for (const CodeGenSchedTransition &Transition : Transitions) {
- dumpIdxVec(Transition.ProcIndices);
+ dbgs() << Transition.ProcIndex << ", ";
}
}
dbgs() << '\n';