}
static void
+nv50_get_compute_state_info(struct pipe_context *pipe, void *hwcso,
+ struct pipe_compute_state_object_info *info)
+{
+ struct nv50_context *nv50 = nv50_context(pipe);
+ struct nv50_program *prog = (struct nv50_program *)hwcso;
+ uint16_t obj_class = nv50->screen->compute->oclass;
+ uint32_t smregs = obj_class >= NVA3_COMPUTE_CLASS ? 16384 : 8192;
+ uint32_t threads = smregs / align(prog->max_gpr, 4);
+
+ info->max_threads = MIN2(ROUND_DOWN_TO(threads, 32), 512);
+ info->private_memory = prog->tls_space;
+ info->preferred_simd_size = 32;
+}
+
+static void
nv50_set_constant_buffer(struct pipe_context *pipe,
enum pipe_shader_type shader, uint index,
bool take_ownership,
pipe->delete_gs_state = nv50_sp_state_delete;
pipe->delete_compute_state = nv50_sp_state_delete;
+ pipe->get_compute_state_info = nv50_get_compute_state_info;
+
pipe->set_blend_color = nv50_set_blend_color;
pipe->set_stencil_ref = nv50_set_stencil_ref;
pipe->set_clip_state = nv50_set_clip_state;