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arm64: dts: reneas: rzg2: Add SDnH clocks
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Wed, 10 Nov 2021 19:15:57 +0000 (20:15 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 19 Nov 2021 09:45:24 +0000 (10:45 +0100)
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-9-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-10-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-11-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-12-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/r8a774a1.dtsi patch | blob | history
arch/arm64/boot/dts/renesas/r8a774b1.dtsi patch | blob | history
arch/arm64/boot/dts/renesas/r8a774c0.dtsi patch | blob | history
arch/arm64/boot/dts/renesas/r8a774e1.dtsi patch | blob | history

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 6f4fffa..f9c4ae6 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -2276,7 +2276,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee100000 0 0x2000>;
                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 314>;
+                       clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 314>;
@@ -2288,7 +2289,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee120000 0 0x2000>;
                        interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 313>;
+                       clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 313>;
@@ -2300,7 +2302,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee140000 0 0x2000>;
                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 312>;
+                       clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 312>;
@@ -2312,7 +2315,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee160000 0 0x2000>;
                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 311>;
+                       clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 311>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 0f7bdfc..0c175b8 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -2133,7 +2133,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee100000 0 0x2000>;
                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 314>;
+                       clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
                        resets = <&cpg 314>;
@@ -2145,7 +2146,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee120000 0 0x2000>;
                        interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 313>;
+                       clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
                        resets = <&cpg 313>;
@@ -2157,7 +2159,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee140000 0 0x2000>;
                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 312>;
+                       clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
                        resets = <&cpg 312>;
@@ -2169,7 +2172,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee160000 0 0x2000>;
                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 311>;
+                       clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
                        resets = <&cpg 311>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index d597772..5e16f6b 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1626,7 +1626,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee100000 0 0x2000>;
                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 314>;
+                       clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
                        resets = <&cpg 314>;
@@ -1638,7 +1639,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee120000 0 0x2000>;
                        interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 313>;
+                       clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
                        resets = <&cpg 313>;
@@ -1650,7 +1652,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee160000 0 0x2000>;
                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 311>;
+                       clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
                        resets = <&cpg 311>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 379a130..673fcc6 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -2362,7 +2362,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee100000 0 0x2000>;
                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 314>;
+                       clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
                        resets = <&cpg 314>;
@@ -2375,7 +2376,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee120000 0 0x2000>;
                        interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 313>;
+                       clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
                        resets = <&cpg 313>;
@@ -2388,7 +2390,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee140000 0 0x2000>;
                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 312>;
+                       clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
                        resets = <&cpg 312>;
@@ -2401,7 +2404,8 @@
                                     "renesas,rcar-gen3-sdhi";
                        reg = <0 0xee160000 0 0x2000>;
                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 311>;
+                       clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;
+                       clock-names = "core", "clkh";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
                        resets = <&cpg 311>;
Domain: System / Kernel;