* "irq" here is the bit number in the system interrupt register to
* separate serial and keyboard interrupts sharing a level.
*/
-void slavio_pic_set_irq(void *opaque, int irq, int level)
+void pic_set_irq_new(void *opaque, int irq, int level)
{
SLAVIO_INTCTLState *s = opaque;
}
}
-void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
+void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
{
SLAVIO_INTCTLState *s = opaque;
DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
if (cpu == (unsigned int)-1) {
- slavio_pic_set_irq(opaque, irq, level);
+ pic_set_irq_new(opaque, irq, level);
return;
}
if (irq < 32) {
#ifdef DEBUG_MISC
#define MISC_DPRINTF(fmt, args...) \
do { printf("MISC: " fmt , ##args); } while (0)
+#define pic_set_irq_new(intctl, irq, level) \
+ do { printf("MISC: set_irq(%d): %d\n", (irq), (level)); \
+ pic_set_irq_new((intctl), (irq),(level));} while (0)
#else
#define MISC_DPRINTF(fmt, args...)
#endif
uint8_t config;
uint8_t aux1, aux2;
uint8_t diag, mctrl, sysctrl;
+ void *intctl;
} MiscState;
#define MISC_MAXADDR 1
MiscState *s = opaque;
if ((s->aux2 & 0x4) && (s->config & 0x8)) {
- pic_set_irq(s->irq, 1);
+ pic_set_irq_new(s->intctl, s->irq, 1);
} else {
- pic_set_irq(s->irq, 0);
+ pic_set_irq_new(s->intctl, s->irq, 0);
}
}
return 0;
}
-void *slavio_misc_init(uint32_t base, int irq)
+void *slavio_misc_init(uint32_t base, int irq, void *intctl)
{
int slavio_misc_io_memory;
MiscState *s;
cpu_register_physical_memory(base + 0xa000000, MISC_MAXADDR, slavio_misc_io_memory);
s->irq = irq;
+ s->intctl = intctl;
register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, s);
qemu_register_reset(slavio_misc_reset, s);
#ifdef DEBUG_SERIAL
#define SER_DPRINTF(fmt, args...) \
do { printf("SER: " fmt , ##args); } while (0)
-#define pic_set_irq(irq, level) \
-do { printf("SER: set_irq(%d): %d\n", (irq), (level)); pic_set_irq((irq),(level));} while (0)
+#define pic_set_irq_new(intctl, irq, level) \
+ do { printf("SER: set_irq(%d): %d\n", (irq), (level)); \
+ pic_set_irq_new((intctl), (irq),(level));} while (0)
#else
#define SER_DPRINTF(fmt, args...)
#endif
uint8_t rx, tx, wregs[16], rregs[16];
SERIOQueue queue;
CharDriverState *chr;
+ void *intctl;
} ChannelState;
struct SerialState {
irq = slavio_serial_update_irq_chn(s);
irq |= slavio_serial_update_irq_chn(s->otherchn);
- pic_set_irq(s->irq, irq);
+ pic_set_irq_new(s->intctl, s->irq, irq);
}
static void slavio_serial_reset_chn(ChannelState *s)
}
-SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2)
+SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1,
+ CharDriverState *chr2, void *intctl)
{
int slavio_serial_io_memory, i;
SerialState *s;
s->chn[i].irq = irq;
s->chn[i].chn = 1 - i;
s->chn[i].type = ser;
+ s->chn[i].intctl = intctl;
if (s->chn[i].chr) {
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
serial_receive1, serial_event, &s->chn[i]);
put_queue(s, 0);
}
-void slavio_serial_ms_kbd_init(int base, int irq)
+void slavio_serial_ms_kbd_init(int base, int irq, void *intctl)
{
int slavio_serial_io_memory, i;
SerialState *s;
s->chn[i].irq = irq;
s->chn[i].chn = 1 - i;
s->chn[i].chr = NULL;
+ s->chn[i].intctl = intctl;
}
s->chn[0].otherchn = &s->chn[1];
s->chn[1].otherchn = &s->chn[0];
#ifdef DEBUG_TIMER
#define DPRINTF(fmt, args...) \
do { printf("TIMER: " fmt , ##args); } while (0)
+#define pic_set_irq_new(intctl, irq, level) \
+ do { printf("TIMER: set_irq(%d): %d\n", (irq), (level)); \
+ pic_set_irq_new((intctl), (irq),(level));} while (0)
#else
#define DPRINTF(fmt, args...)
#endif
int reached, stopped;
int mode; // 0 = processor, 1 = user, 2 = system
unsigned int cpu;
+ void *intctl;
} SLAVIO_TIMERState;
#define TIMER_MAXADDR 0x1f
DPRINTF("irq %d limit %d reached %d d %" PRId64 " count %d s->c %x diff %" PRId64 " stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode);
if (s->mode != 1)
- pic_set_irq_cpu(s->irq, out, s->cpu);
+ pic_set_irq_cpu(s->intctl, s->irq, out, s->cpu);
}
// timer callback
// part of counter (user mode)
if (s->mode != 1) {
// clear irq
- pic_set_irq_cpu(s->irq, 0, s->cpu);
+ pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
s->reached = 0;
return s->limit;
}
slavio_timer_get_out(s);
}
-void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu)
+void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu,
+ void *intctl)
{
int slavio_timer_io_memory;
SLAVIO_TIMERState *s;
s->mode = mode;
s->cpu = cpu;
s->irq_timer = qemu_new_timer(vm_clock, slavio_timer_irq, s);
+ s->intctl = intctl;
slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
slavio_timer_mem_write, s);
void pic_set_irq(int irq, int level)
{
- slavio_pic_set_irq(slavio_intctl, irq, level);
-}
-
-void pic_set_irq_new(void *opaque, int irq, int level)
-{
- pic_set_irq(irq, level);
-}
-
-void pic_set_irq_cpu(int irq, int level, unsigned int cpu)
-{
- slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu);
+ pic_set_irq_new(slavio_intctl, irq, level);
}
static void *slavio_misc;
nvram = m48t59_init(0, hwdef->nvram_base, 0, hwdef->nvram_size, 8);
for (i = 0; i < MAX_CPUS; i++) {
slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE,
- hwdef->clock_irq, 0, i);
+ hwdef->clock_irq, 0, i, slavio_intctl);
}
slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2,
- (unsigned int)-1);
- slavio_serial_ms_kbd_init(hwdef->ms_kb_base, hwdef->ms_kb_irq);
+ (unsigned int)-1, slavio_intctl);
+ slavio_serial_ms_kbd_init(hwdef->ms_kb_base, hwdef->ms_kb_irq,
+ slavio_intctl);
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
slavio_serial_init(hwdef->serial_base, hwdef->ser_irq,
- serial_hds[1], serial_hds[0]);
+ serial_hds[1], serial_hds[0], slavio_intctl);
fdctrl_init(hwdef->fd_irq, 0, 1, hwdef->fd_base, fd_table);
main_esp = esp_init(bs_table, hwdef->esp_base, dma);
}
}
- slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->me_irq);
+ slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->me_irq,
+ slavio_intctl);
cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
sparc32_dma_set_reset_data(dma, main_esp, main_lance);
}
/* sun4m.c */
extern QEMUMachine ss5_machine, ss10_machine;
-void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
/* iommu.c */
void *iommu_init(uint32_t addr);
unsigned long vram_offset, int vram_size, int width, int height);
/* slavio_intctl.c */
+void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
const uint32_t *intbit_to_level);
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
/* slavio_timer.c */
-void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu);
+void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu,
+ void *intctl);
/* slavio_serial.c */
-SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2);
-void slavio_serial_ms_kbd_init(int base, int irq);
+SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1,
+ CharDriverState *chr2, void *intctl);
+void slavio_serial_ms_kbd_init(int base, int irq, void *intctl);
/* slavio_misc.c */
-void *slavio_misc_init(uint32_t base, int irq);
+void *slavio_misc_init(uint32_t base, int irq, void *intctl);
void slavio_set_power_fail(void *opaque, int power_failing);
/* esp.c */