arm64: Add AMPERE1 to the Spectre-BHB affected list
authorD Scott Phillips <scott@os.amperecomputing.com>
Tue, 11 Oct 2022 02:21:40 +0000 (19:21 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 3 Nov 2022 14:59:20 +0000 (23:59 +0900)
[ Upstream commit 0e5d5ae837c8ce04d2ddb874ec5f920118bd9d31 ]

Per AmpereOne erratum AC03_CPU_12, "Branch history may allow control of
speculative execution across software contexts," the AMPERE1 core needs the
bhb clearing loop to mitigate Spectre-BHB, with a loop iteration count of
11.

Signed-off-by: D Scott Phillips <scott@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20221011022140.432370-1-scott@os.amperecomputing.com
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/include/asm/cputype.h
arch/arm64/kernel/proton-pack.c

index 39f5c16..457b6bb 100644 (file)
@@ -60,6 +60,7 @@
 #define ARM_CPU_IMP_FUJITSU            0x46
 #define ARM_CPU_IMP_HISI               0x48
 #define ARM_CPU_IMP_APPLE              0x61
+#define ARM_CPU_IMP_AMPERE             0xC0
 
 #define ARM_CPU_PART_AEM_V8            0xD0F
 #define ARM_CPU_PART_FOUNDATION                0xD00
 #define APPLE_CPU_PART_M1_ICESTORM     0x022
 #define APPLE_CPU_PART_M1_FIRESTORM    0x023
 
+#define AMPERE_CPU_PART_AMPERE1                0xAC3
+
 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
 #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
 #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
+#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
 
 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
 #define MIDR_FUJITSU_ERRATUM_010001            MIDR_FUJITSU_A64FX
index 40be3a7..428cfab 100644 (file)
@@ -868,6 +868,10 @@ u8 spectre_bhb_loop_affected(int scope)
                        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
                        {},
                };
+               static const struct midr_range spectre_bhb_k11_list[] = {
+                       MIDR_ALL_VERSIONS(MIDR_AMPERE1),
+                       {},
+               };
                static const struct midr_range spectre_bhb_k8_list[] = {
                        MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
                        MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
@@ -878,6 +882,8 @@ u8 spectre_bhb_loop_affected(int scope)
                        k = 32;
                else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list))
                        k = 24;
+               else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list))
+                       k = 11;
                else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list))
                        k =  8;