Merge in v2022.07-rc5.
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
+dtb-$(CONFIG_BCM47622) += \
+ bcm947622.dtb
+
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
+dtb-$(CONFIG_STM32MP13x) += \
+ stm32mp135f-dk.dtb
+
dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp15xx-dhcom-drc02.dtb \
stm32mp15xx-dhcom-pdk2.dtb \
stm32mp15xx-dhcom-picoitx.dtb \
- stm32mp15xx-dhcor-avenger96.dtb
+ stm32mp15xx-dhcor-avenger96.dtb \
+ stm32mp15xx-dhcor-drc-compact.dtb
dtb-$(CONFIG_SOC_K3_AM6) += \
k3-am654-base-board.dtb \
k3-am642-sk.dtb \
k3-am642-r5-sk.dtb
+dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
+ k3-am625-r5-sk.dtb
+
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x950000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x980000
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+ CONFIG_CMD_DHCP=y
+ CONFIG_CMD_MII=y
+ CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
+ CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+ CONFIG_DM_ETH_PHY=y
+ CONFIG_PHY_GIGE=y
+ CONFIG_FEC_MXC=y
+ CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
+ CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_MAXARGS=32
+CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
+ CONFIG_PHY_ADIN=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x3db00
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x30000000
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
+CONFIG_SPL_TARGET="u-boot.itb"
CONFIG_SYS_PROMPT="STM32MP> "
+CONFIG_SYS_PBSIZE=1050
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_EEPROM=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_DWC_ETH_QOS=y
+ CONFIG_KS8851_MLL=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_STM32_USBPHYC=y
set of generic read, write and ioctl methods may be used to
access the device.
+config NVMEM
+ bool "NVMEM support"
+ help
+ This adds support for a common interface to different types of
+ non-volatile memory. Consumers can use nvmem-cells properties to look
+ up hardware configuration data such as MAC addresses and calibration
+ settings.
+
+config SPL_NVMEM
+ bool "NVMEM support in SPL"
+ help
+ This adds support for a common interface to different types of
+ non-volatile memory. Consumers can use nvmem-cells properties to look
+ up hardware configuration data such as MAC addresses and calibration
+ settings.
+
config ALTERA_SYSID
bool "Altera Sysid support"
depends on MISC
config SPL_CROS_EC
bool "Enable Chrome OS EC in SPL"
- depends on SPL
+ depends on SPL_MISC
help
Enable access to the Chrome OS EC in SPL. This is a separate
microcontroller typically available on a SPI bus on Chromebooks. It
config TPL_CROS_EC
bool "Enable Chrome OS EC in TPL"
- depends on TPL
+ depends on TPL_MISC
help
Enable access to the Chrome OS EC in TPL. This is a separate
microcontroller typically available on a SPI bus on Chromebooks. It
config VPL_CROS_EC
bool "Enable Chrome OS EC in VPL"
- depends on VPL
+ depends on VPL_MISC
help
Enable access to the Chrome OS EC in VPL. This is a separate
microcontroller typically available on a SPI bus on Chromebooks. It
config SPL_CROS_EC_LPC
bool "Enable Chrome OS EC LPC driver in SPL"
- depends on CROS_EC
+ depends on CROS_EC && SPL_MISC
help
Enable I2C access to the Chrome OS EC. This is used on x86
Chromebooks such as link and falco. The keyboard is provided
config TPL_CROS_EC_LPC
bool "Enable Chrome OS EC LPC driver in TPL"
- depends on CROS_EC
+ depends on CROS_EC && TPL_MISC
help
Enable I2C access to the Chrome OS EC. This is used on x86
Chromebooks such as link and falco. The keyboard is provided
config VPL_CROS_EC_LPC
bool "Enable Chrome OS EC LPC driver in VPL"
- depends on CROS_EC
+ depends on CROS_EC && VPL_MISC
help
Enable I2C access to the Chrome OS EC. This is used on x86
Chromebooks such as link and falco. The keyboard is provided
help
This selects support for the eFUSE on Ingenic JZ4780 SoCs.
+config LS2_SFP
+ bool "Layerscape Security Fuse Processor"
+ depends on FSL_LSCH2 || ARCH_LS1021A
+ depends on MISC
+ imply DM_REGULATOR
+ help
+ This adds support for the Security Fuse Processor found on Layerscape
+ SoCs. It contains various fuses related to secure boot, including the
+ Super Root Key hash, One-Time-Programmable Master Key, Debug
+ Challenge/Response values, and others. Fuses are numbered according
+ to their four-byte offset from the start of the bank.
+
+ If you don't need to read/program fuses, say 'n'.
+
config MXC_OCOTP
bool "Enable MXC OCOTP Driver"
depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
config SPL_MXC_OCOTP
bool "Enable MXC OCOTP driver in SPL"
- depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
+ depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
default y
help
If you say Y here, you will get support for the One Time
config SPL_P2SB
bool "Intel Primary to Sideband Bridge in SPL"
- depends on SPL && (X86 || SANDBOX)
+ depends on SPL_MISC && (X86 || SANDBOX)
help
The Primary to Sideband Bridge is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
config TPL_P2SB
bool "Intel Primary to Sideband Bridge in TPL"
- depends on TPL && (X86 || SANDBOX)
+ depends on TPL_MISC && (X86 || SANDBOX)
help
The Primary to Sideband Bridge is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
config SPL_PWRSEQ
bool "Enable power-sequencing drivers for SPL"
- depends on PWRSEQ
+ depends on SPL_MISC && PWRSEQ
help
Power-sequencing drivers provide support for controlling power for
devices. They are typically referenced by a phandle from another
model. This should only be enabled for testing as it is not useful for
anything else.
+ config USB_HUB_USB251XB
+ tristate "USB251XB Hub Controller Configuration Driver"
+ depends on I2C
+ help
+ This option enables support for configuration via SMBus of the
+ Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
+ parameters may be set in devicetree or platform data.
+ Say Y or M here if you need to configure such a device via SMBus.
+
config TWL4030_LED
bool "Enable TWL4030 LED controller"
help
config SPL_I2C_EEPROM
bool "Enable driver for generic I2C-attached EEPROMs for SPL"
- depends on MISC && SPL && SPL_DM
+ depends on SPL_MISC
help
This option is an SPL-variant of the I2C_EEPROM option.
See the help of I2C_EEPROM for details.
config SPL_FS_LOADER
bool "Enable loader driver for file system"
+ depends on SPL
help
This is file system generic loader which can be used to load
the file image from the storage into target such as memory.
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_$(SPL_TPL_)MISC) += misc-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)NVMEM) += nvmem.o
obj-$(CONFIG_$(SPL_TPL_)CROS_EC) += cros_ec.o
obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o
ifdef CONFIG_$(SPL_)DM_I2C
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
+ obj-$(CONFIG_USB_HUB_USB251XB) += usb251xb.o
endif
endif
ifdef CONFIG_SPL_OF_PLATDATA
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
+obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o
obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
if (sqfs_disk_read(0, 1, *sblk) != 1) {
free(*sblk);
- sblk = NULL;
+ *sblk = NULL;
return -EINVAL;
}
int i_number, offset = 0, ret;
struct fs_dirent *dent;
unsigned char *ipos;
+ u16 name_size;
dirs = (struct squashfs_dir_stream *)fs_dirs;
if (!dirs->size) {
return -SQFS_STOP_READDIR;
}
- /* Set entry name */
- strncpy(dent->name, dirs->entry->name, dirs->entry->name_size + 1);
- dent->name[dirs->entry->name_size + 1] = '\0';
+ /* Set entry name (capped at FS_DIRENT_NAME_LEN which is a U-Boot limitation) */
+ name_size = min_t(u16, dirs->entry->name_size + 1, FS_DIRENT_NAME_LEN - 1);
+ strncpy(dent->name, dirs->entry->name, name_size);
+ dent->name[name_size] = '\0';
offset = dirs->entry->name_size + 1 + SQFS_ENTRY_BASE_LENGTH;
dirs->entry_count--;
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
-
/* USB */
#define CONFIG_USB_EHCI_EXYNOS
"rootfstype=ext4\0" \
"console=console=ttySAC2,115200n8\0" \
"fdtfile=exynos5422-odroidxu3.dtb\0" \
+ "board=odroid\0" \
"board_name=odroidxu3\0" \
"mmcbootdev=0\0" \
"mmcrootdev=0\0" \
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_STACK 0x920000
-#define CONFIG_SPL_BSS_START_ADDR 0x910000
-#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
-#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
-#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
-
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
-#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_board=dev\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
- "setup=setenv setupargs console=${console},${baudrate} " \
- "console=tty1 consoleblank=0 earlycon\0" \
+ "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
+ "consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#if defined(CONFIG_ENV_IS_IN_MMC)
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
-/* UART */
-#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-
-/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE SZ_2K
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-
/* ENET */
#define CONFIG_FEC_MXC_PHYADDR 7
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SPL_MAX_SIZE (152 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_STACK 0x960000
-#define CONFIG_SPL_BSS_START_ADDR 0x0098fc00
-#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
-#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
-#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x184000
/* For RAW image gives a error info not panic */
-#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#define CONFIG_POWER_PCA9450
"fdt_board=dev\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
- "setup=setenv setupargs console=${console},${baudrate} console=tty1 " \
+ "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
"consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G)
-/* UART */
-#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
-
-/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE SZ_2K
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-
#endif /* __VERDIN_IMX8MP_H */
projects / platform / kernel / u-boot.git / commitdiff