UART: G12A: verify all uart port on skt dts.[1/1]
authorqi duan <qi.duan@amlogic.com>
Thu, 1 Feb 2018 11:55:48 +0000 (19:55 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Fri, 2 Mar 2018 07:07:52 +0000 (15:07 +0800)
PD#156734: UART: G12A: verify all uart port on skt dts.

Change-Id: I2fb272d7803d0c21e16a10c3ccb535b4244e6e6b
Signed-off-by: qi duan <qi.duan@amlogic.com>
arch/arm64/boot/dts/amlogic/g12a_skt.dts
arch/arm64/boot/dts/amlogic/mesong12a.dtsi
drivers/amlogic/uart/meson_uart.c

index fa25ea5..5e0ade7 100644 (file)
 
        aliases {
                serial0 = &uart_AO;
+               serial1 = &uart_A;
+               serial2 = &uart_B;
+               serial3 = &uart_C;
+               serial4 = &uart_AO_B;
        };
 
        memory@00000000 {
                };
        };
 
+       uart_A: serial@ffd24000 {
+               compatible = "amlogic, meson-uart";
+               reg = <0x0 0xffd24000 0x0 0x18>;
+               interrupts = <0 26 1>;
+               status = "disable";
+               clocks = <&xtal
+                       &clkc CLKID_UART0>;
+               clock-names = "clk_uart",
+                       "clk_gate";
+               fifosize = < 128 >;
+               pinctrl-names = "default";
+               pinctrl-0 = <&a_uart_pins>;
+       };
+
+       uart_B: serial@ffd23000 {
+               compatible = "amlogic, meson-uart";
+               reg = <0x0 0xffd23000 0x0 0x18>;
+               interrupts = <0 75 1>;
+               status = "disable";
+               clocks = <&xtal
+                       &clkc CLKID_UART1>;
+               clock-names = "clk_uart",
+                       "clk_gate";
+               fifosize = < 64 >;
+               pinctrl-names = "default";
+               pinctrl-0 = <&b_uart_pins>;
+       };
+
+       uart_C: serial@ffd22000 {
+               compatible = "amlogic, meson-uart";
+               reg = <0x0 0xffd22000 0x0 0x18>;
+               interrupts = <0 93 1>;
+               status = "disable";
+               clocks = <&xtal
+                       &clkc CLKID_UART1>;
+               clock-names = "clk_uart",
+                       "clk_gate";
+               fifosize = < 64 >;
+               pinctrl-names = "default";
+               pinctrl-0 = <&c_uart_pins>;
+       };
+
        canvas{
                compatible = "amlogic, meson, canvas";
                dev_name = "amlogic-canvas";
                status = "okay";
                clocks = <&xtal>;
                clock-names = "clk_uart";
-               xtal_tick_en = <1>;
+               xtal_tick_en = <2>;
                fifosize = < 64 >;
                pinctrl-names = "default";
                pinctrl-0 = <&ao_uart_pins>;
                support-sysrq = <0>;    /* 0 not support , 1 support */
        };
+
+       uart_AO_B: serial@4000 {
+               compatible = "amlogic, meson-uart";
+               reg = <0x0 0x4000 0x0 0x18>;
+               interrupts = <0 197 1>;
+               status = "disable";
+               clocks = <&xtal>;
+               clock-names = "clk_uart";
+               fifosize = < 64 >;
+               pinctrl-names = "default";
+               pinctrl-0 = <&ao_b_uart_pins>;
+       };
 };
index f4e79cf..9cc6274 100644 (file)
                        function = "uart_ao_a";
                };
        };
+
+       ao_b_uart_pins:ao_b_uart {
+               mux {
+                       groups = "uart_ao_tx_b_2",
+                               "uart_ao_rx_b_3";
+                       function = "uart_ao_b";
+               };
+       };
 };
 
 &pinctrl_periphs {
                        bias-pull-up;
                };
        };
+
+       a_uart_pins:a_uart {
+               mux {
+                       groups = "uart_tx_a",
+                               "uart_rx_a";
+                       function = "uart_a";
+               };
+       };
+
+       b_uart_pins:b_uart {
+               mux {
+                       groups = "uart_tx_b",
+                               "uart_rx_b";
+                       function = "uart_b";
+               };
+       };
+
+       c_uart_pins:c_uart {
+               mux {
+                       groups = "uart_tx_c",
+                               "uart_rx_c";
+                       function = "uart_c";
+               };
+       };
 };
index 70b5a63..b86ef6e 100644 (file)
@@ -92,6 +92,8 @@
 #define AML_UART_BAUD_USE              BIT(23)
 #define AML_UART_BAUD_XTAL             BIT(24)
 #define AML_UART_BAUD_XTAL_TICK        BIT(26)
+#define AML_UART_BAUD_XTAL_DIV2        BIT(27)
+
 
 #define AML_UART_PORT_MAX              16
 #define AML_UART_DEV_NAME              "ttyS"
@@ -552,9 +554,15 @@ static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
                        dev_info(&pdev->dev, "ttyS%d use xtal(24M) %d change %ld to %ld\n",
                                port->line, port->uartclk,
                                mup->baud, baud);
-                       val = (port->uartclk + baud / 2) / baud  - 1;
-                       val |= (AML_UART_BAUD_USE|AML_UART_BAUD_XTAL
-                               |AML_UART_BAUD_XTAL_TICK);
+                       if (xtal_tick_en == 1) {
+                               val = (port->uartclk + baud / 2) / baud  - 1;
+                               val |= (AML_UART_BAUD_USE|AML_UART_BAUD_XTAL
+                                       |AML_UART_BAUD_XTAL_TICK);
+                       } else if (xtal_tick_en == 2) {
+                               val = (port->uartclk/2 + baud / 2) / baud  - 1;
+                               val |= (AML_UART_BAUD_USE|AML_UART_BAUD_XTAL
+                                       |AML_UART_BAUD_XTAL_DIV2);
+                       }
                } else {
                        dev_info(&pdev->dev, "ttyS%d use xtal(8M) %d change %ld to %ld\n",
                                port->line, port->uartclk,
@@ -1103,10 +1111,12 @@ static int meson_uart_probe(struct platform_device *pdev)
 
        if (!xtal_tick_en) {
                prop = of_get_property(pdev->dev.of_node, "xtal_tick_en", NULL);
-               if (prop)
+               if (prop) {
                        xtal_tick_en = of_read_ulong(prop, 1);
+                       if (xtal_tick_en == 1)
+                               xtal_tick_en = 0;
+               }
        }
-       xtal_tick_en = 0;
 
        port->iotype = UPIO_MEM;
        port->mapbase = res_mem->start;